Video IP

This brief specification describes the operation of the HD Multi-window Video Processor (evaluation) IP Core.
The IP Core is provided as a netlist in either EDIF, Verilog or VHDL formats.

The TXT_OVERLAY IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video.
The module supports a wide range of text effects and the programming interface is very simple.
Text is written to a character buffer which is mapped (via a bitmap ROM) directly to the display.

The ALIAS_FILTER IP Core is a fully pipelined anti-aliasing filter for use in digital video applications.
The design implements a low pass filter response on the source video in order to alleviate problems such as jagged edges, stepped lines and Moiré interference patterns.
This is especially important when downscaling and upscaling video by large factors.

XY2_SCALER is a very high quality video scaler capable of generating interpolated output images from 16x16 up to 216 x 216 pixels in resolution.
The architecture permits seamless scaling (either up or down) depending on the chosen scale factor.
Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points.
All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics.

The NVP300, AI-based Neural Video Processing IP push video quality to the next level by leveraging the advanced features and benefits of AI based video processing technologies.
The NVP300 IP features an optimized hardware implementation to deliver real-time AI processing of 4K video whithin best-in-class silicon area and power budget suitable for embedded products.

Advanced Professional Video, APV, CODEC is a next generation of video compression & decompression tool and key technology for prosumers who do not want to compromise on quality while enjoying the convenience of video capture and edit experience using edge devices such as smartphone, tablet, laptop, etc.
To ensure the over-the-horizon video experience with extreme visual quality, APV CODEC works with up to 10- and 12-bit YUV in 422&444 format.

The E300 Series of Encoder IP features a new hardware architecture that minimizes the silicon area while enabling 4K resolution encoding in a single core and beyond in a multi-core configuration.
The E300 Series Encoder is built around a true multi format architecture that shares resources between the H.264, H.265, VP9, AV1, JPEG, VVC compression standards, while providing superior video encoding quality.

‘Pulsar-AV1’ is a fully hardwired AV1 video encoder IP that offers high computational and compression efficiency beyond customer-grade.

The Intel® FPGA Video and Vision Processing Suite is a collection of next-generation Intel® FPGA intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs
These Intel® FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as studio broadcast, video conferencing, AV networking, medical imaging, industrial inspections and robotics, smart city/retail and consumer.

The Intel FPGA Video and Image Processing Suite is a collection of Intel FPGA intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs
These Intel FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as studio broadcast, video conferencing, AV networking, medical imaging, smart city/retail, and consumer.