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USB 4.0 IP

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Compare 170 IP from 19 vendors (1 - 10)
  • USB 2.0 PHY TSMC 40LPeDRAM
    • Complies with USB specifications, rev. 2.0 and 1.1
    • Complies with UTMI+ specification, level 3, rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
  • USB 2.0 PHY TSMC 40LP
    • Complies with USB specifications, rev. 2.0 and 1.1
    • Complies with UTMI+ specification, level 3, rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
  • USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)
    • Smallest USB 3.2 Gen1x1 BCK PHY IP worldwide (e.g. IP size @40nm <0.36mm²)
    • Fully compliant with Universal Serial Bus USB 3.2 Gen1x1, 2.0, and 1.1 electrical specifications
    • Supports clock outputs from the internal BCK module
    • Real-time calibrations to ensure frequency accuracy
  • USB 2.0 PHY TSMC 40G
    • Complies with USB specifications, rev. 2.0 and 1.1
    • Complies with UTMI+ specification, level 3, rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
  • USB 3.0 PHY IP, Silicon Proven in TSMC 40LP
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in TSMC 40LP
  • USB 2.0 PHY IP, Silicon Proven in UMC 40LP
    • Compliant with USB2.0 and USB1.1 specification
    • Compliant with UTMI Specification Version level 3.
    • Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
    • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
    Block Diagram -- USB 2.0 PHY IP, Silicon Proven in UMC 40LP
  • USB 3.0 PHY IP, Silicon Proven in UMC 40SP
    • Compliant with Universal Serial Bus 3.0 Specification
    • Supports 2.5GT/s and 5.0GT/s serial data transmission rate
    • Compliant with PIPE 3.0
    • Compliant with Universal Serial Bus 2.0 Specification
    Block Diagram -- USB 3.0 PHY IP, Silicon Proven in UMC 40SP
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