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USB 3 IP

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Compare 599 IP from 50 vendors (1 - 10)
  • USB 3.2 Dual Role Device (DRD) Controller
    • USB 3.2 Dual Role Device (DRD) softcore semiconductor IP is designed for applications requiring both USB Host and Device implementation.
    • This core comprises USB3.2 SSP, SS, HS/FS/LS Host, and Device controllers in a single codebase that supports role-swap functionality
  • USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
    • XtremeSilica’s USB 3.2 Verification IP offers a comprehensive solution for validating designs based on the USB 3.2 specification. It supports SuperSpeed+ data rates up to 20 Gbps, ensuring protocol compliance, power management, and seamless interoperability across versions.
    • The product’s advanced features include dynamic link negotiation validation, error injection, and robust debugging tools. It enables testing across a range of devices, ensuring high-speed data transfer and reliable performance in both legacy and modern USB designs
    Block Diagram -- USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
  • USB 3.2 Verification IP
    • Fully compliant with USB 3.2 specification version 1.1, xHCI Specification Revision 1.2, and Pipe Interface 6.1.1 with Message Bus Interface for USB3.2 Architecture with backward compatibility to USB3.1, USB3.0 and USB2.0 (including USB2.0, USB 3.0. OTG)
    • Supports USB Type-C.
    • Supports up to 128 devices including hub and device on any tier level.
    • Supports 15 IN and 15 OUT and 1 control endpoint for each device.
    Block Diagram -- USB 3.2 Verification IP
  • USB 3.1 Cable Marker IP
    • The OTC9115 is a complete, low cost, single chip cable marker for USB PD Type-C (baseband) cables.
    • In low silicon area and just 4 IOs, the device has been designed exclusively for very high volume Type-C cables with basic marker requirements.
    Block Diagram -- USB 3.1 Cable Marker IP
  • USB 3.0/3.1/3.2/SSIC Verification IP
    • Compliant with USB 3.0/3.1/3.2 specification version 1.0
    • Supports Superspeed USB 3.0, SuperSpeedPlus 3.1 , USB 3.2 and 3.0 OTG
    • Complete solution for thorough chip-level verification
    • Comprehensive model support a Host, Device, Hub, PHY
    Block Diagram -- USB 3.0/3.1/3.2/SSIC Verification IP
  • USB3.x OTG IIP
    • USB 3.0/3.1/3.2 Common support
    • Compliant with USB 3.0/3.1/3.2 specification
    • Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2
    • Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
    Block Diagram -- USB3.x OTG IIP
  • USB3.x HUB IIP
    • USB 3.0/3.1/3.2 Common support
    • Compliant with USB 3.0/3.1/3.2 specification
    • Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2
    • Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
    Block Diagram -- USB3.x HUB IIP
  • USB3.x DEVICE IIP
    • USB 3.0/3.1/3.2 Common support
    • Compliant with USB 3.0/3.1/3.2 specification
    • Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2
    • Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
    Block Diagram -- USB3.x DEVICE IIP
  • USB 3.2 Verification IP
    • Fully compliant with USB 3.2 specification version 1.1, xHCI Specification Revision 1.2, and Pipe Interface 6.1.1 with Message Bus Interface for USB3.2 Architecture with backward compatibility to USB3.1, USB3.0 and USB2.0 (including USB2.0, USB 3.0. OTG)
    • Supports USB Type-C.
    • Supports up to 128 devices including hub and device on any tier level.
    • Supports 15 IN and 15 OUT and 1 control endpoint for each device.
    Block Diagram -- USB 3.2 Verification IP
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