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USB 2 IP

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Compare 630 IP from 53 vendors (1 - 10)
  • USB 3.1 SuperSpeed+ (Gen2) Embedded Host Controller (USB-IF Certfied)
    • USB-IF Certified full-feature Embedded Host Controller solution
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 3.1 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
    Block Diagram -- USB 3.1 SuperSpeed+ (Gen2) Embedded Host Controller (USB-IF Certfied)
  • USB 3.1 SuperSpeed+ (Gen2) Dual-Role Device Controller (USB-IF Certified)
    • USB-IF Certified full-feature Dual Role Device Controller solution
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 3.1 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
    Block Diagram -- USB 3.1 SuperSpeed+ (Gen2) Dual-Role Device Controller (USB-IF Certified)
  • USB 3.1 SuperSpeed+ (Gen2) Device Controller (USB-IF Certified)
    • USB-IF Certified full-feature Device Controller solution.
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 3.1 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
    Block Diagram -- USB 3.1 SuperSpeed+ (Gen2) Device Controller (USB-IF Certified)
  • USB 3.1 SuperSpeed+ (Gen2) PC Host Controller (USB-IF Certified)
    • USB-IF Certified full-feature PC Host Controller solution
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 3.1 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
    Block Diagram -- USB 3.1 SuperSpeed+ (Gen2) PC Host Controller (USB-IF Certified)
  • AXI 2.0 USB Device IP
    • AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
    • USB serial interface engine implemented to support USB2.0 full speed and high speed interface
    • Supports ULPI interface to external PHY chip
    • Supports control, bulk, interrupt and isochronous transfers on USB interface
  • USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power
    • Configuration options to maximize performance and minimize CPU interrupts
    • Flexible parameters enable easy integration into low and high-latency systems
    • Transfer- or transaction-based processing of USB data based on system requirements
    • Configurable data buffering options to fine-tune performance/ area trade-offs
    Block Diagram -- USB 2.0 Hi-Speed OTG Controller version 4 with Active Clock Gating to save active power
  • USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
    • Configuration options to maximize performance and minimize CPU interrupts
    • Flexible parameters enable easy integration into low and high-latency systems
    • Transfer- or transaction-based processing of USB data based on system requirements
    • Configurable data buffering options to fine-tune performance/ area trade-offs
    Block Diagram -- USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
  • USB 2.0 Device Controller version 4 with Active Clock Gating to save active power
    • Configuration options to maximize performance and minimize CPU interrupts
    • Flexible parameters enable easy integration into low and high-latency systems
    • Transfer- or transaction-based processing of USB data based on system requirements
    • Configurable data buffering options to fine-tune performance/ area trade-offs
    Block Diagram -- USB 2.0 Device Controller version 4 with Active Clock Gating to save active power
  • USB 2.0 nanoPHY - UMC 65SP, OTG
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 nanoPHY - UMC 65SP, OTG
  • USB 2.0 picoPHY - UMC 40LP25, OTG
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 picoPHY - UMC 40LP25, OTG
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