Trilinear Technologies IP
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6
IP
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6)
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MST Topology Management Stack
- DisplayPort 1.4/2.0 compliant
- Fully portable embedded C
- Auto enumeration and stream management
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HDCP Encryption-Decryption Engine
- Real-time encryption/decryption
- 8k compression available for select applications
- Low gate count and low latency implementation
- Supports HDCP 1.3 and 1.4
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Display Stream Compression (DSC 1.2) Encoder
- VESA DSC 1.2 Compliant
- Capable of encoding up to 4K video at 30fps in FPGA and ASIC
- 8K compression available for select applications
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Display Stream Compression (DSC 1.2) Decoder
- VESA DSC 1.2 Compliant
- Capable of decoding 4K video at 30fps in FPGA and ASIC
- Decode 8K video at 30fps in ASIC applications
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DisplayPort Transmitter Link Controller
- Silicon proven on multiple ASIC and FPGA processes with multiple PHY partners.
- 1, 2 or 4 pixels per input cycle, supporting up to 16K resolution input per source
- 1.62-8.1Gbps link rate across 1,2, or 4 lanes
- SST or MST operation
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DisplayPort Receiver Link Controller
- Silicon proven on multiple ASIC and FPGA processes
- Capable of operating without a host CPU in low complexity applications
- Horizontal and vertical video delimiter signals with 1, 2 or 4 pixels per output cycle, supporting up to 16K resolution output; deep color and HDR support
- 1.62 to 8.1 Gbps link rate across 1, 2, or 4 lanes
