TCPHardware Accelerator IP

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Compare 437 IP from 83 vendors (1 - 10)
  • Asymmetric cryptographic accelerator
    • The ACrypto Engine is an asymmetric cryptographic accelerator suitable for embedded application.
    • It provides capability for basic arithmetic and frequently used operations. Along with driver, it is flexible to support popular upperlayer applications.
  • Graphic 2D Accelerator
    • The Graphic 2D Accelerator (G2D) is a specialized DMA dedicated to image manipulation.
  • Neural Network Accelerator
    • The Neural-Network Accelerators (NACC) improves the inference performance of neural networks.
    • The NACC data type is INT8, and supports im2col, convolution, depthwise convolution, average pool, max pool, fully connected, activation and matrix multiplication acceleration.
  • APB Post-Quantum Cryptography Accelerator IP Core
    • Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).
    • The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.
    Block Diagram -- APB Post-Quantum Cryptography Accelerator IP Core
  • Very fast VMAF accelerator
    • It measures VMAF, a video quality metric, faster than open source.
  • AI/ML Accelerator
    • General purpose RISC-V core (RV32IMC)
    • Standard communication peripherals: UART, I2C, SPI (x2), Octo-SPI, DCMI, I2S
    • JTAG debugging interface
    • Up to 4 MB of on-chip SRAM + 0.5MB of MRAM
    • Multi neural network execution
    Block Diagram -- AI/ML Accelerator
  • BitBLT Graphics Hardware Accelerator (Avalon Bus)
    • The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
    • A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
    Block Diagram -- BitBLT Graphics Hardware Accelerator (Avalon Bus)
  • 2D Graphics Hardware Accelerator (AHB Bus)
    • Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
    • Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
    • Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
    • Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
    Block Diagram -- 2D Graphics Hardware Accelerator (AHB Bus)
  • 2D Graphics Hardware Accelerator (AXI Bus)
    • Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
    • Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
    • Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
    • Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
    Block Diagram -- 2D Graphics Hardware Accelerator (AXI Bus)
  • TCP/UDP/IP Network Protocol Accelerator Platform
    • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
    • Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
    • 128-bit wide bi-directional data paths with streaming interfaces
    • Multiple, parallel TCP engines for scalable processing
    Block Diagram -- TCP/UDP/IP Network Protocol  Accelerator Platform
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Semiconductor IP