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TCPHardware Accelerator IP

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Compare 420 IP from 85 vendors (1 - 10)
  • BitBLT Graphics Hardware Accelerator (Avalon Bus)
    • The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
    • A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
    Block Diagram -- BitBLT Graphics Hardware Accelerator (Avalon Bus)
  • 2D Graphics Hardware Accelerator (AHB Bus)
    • Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
    • Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
    • Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
    • Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
    Block Diagram -- 2D Graphics Hardware Accelerator (AHB Bus)
  • 2D Graphics Hardware Accelerator (AXI Bus)
    • Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
    • Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
    • Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
    • Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit
    Block Diagram -- 2D Graphics Hardware Accelerator (AXI Bus)
  • TCP/UDP/IP Network Protocol Accelerator Platform
    • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
    • Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
    • 128-bit wide bi-directional data paths with streaming interfaces
    • Multiple, parallel TCP engines for scalable processing
    Block Diagram -- TCP/UDP/IP Network Protocol Accelerator Platform
  • Agile Post Quantum Crypto (PQC) Public Key Accelerator - NIST algorithms
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • Agile ECC/RSA Public Key Accelerator with 32-bit ALU
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • Agile ECC/RSA Public Key Accelerator with 128-bit ALU
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • Multipurpose Security Protocol Accelerator
    • Highly configurable security accelerator
    • Support for all ciphers, hashes and MAC algorithms used in major protocols such as IPsec, SSL/TLS/DTLS, Wi-Fi, 3GPP LTE/LTE-A, SRTP, MACsec
    • Cipher algorithms: AES, DES/3DES, ChaCha20, MULTI2, KASUMI, SNOW 3G, ZUC
    • Cipher modes: ECB, CBC, CTR, OFB, CFB, f8, XTS, UEA1, UEA2, 128-EEA1, 128-EEA2, 128-EEA3
  • Security Protocol Accelerator for SM3 and SM4 Ciphers
    • Highly customer configurable, silicon-proven security accelerator
    • Support for Chinese security SM3 and SM4 (modes: ECB, CTR, CBC, CCM, GCM, XTS) algorithms
    • Option: Differential Power Analysis (DPA) countermeasures for SM4
    • Built-in scatter/gather DMA capability offloads the host processor
  • Public Key Accelerator
    • Modular exponentiation operations with up to 4096-bit modulus
    • Prime field ECC operations with up to 571-bit modulus
    • Fastest implementation is 58 kGE and 68 Op/s for 2048-bit RSA, 431 Op/s for 1024-bit RSA, 150 Op/s for 384-bit scalar multiplication
    Block Diagram -- Public Key Accelerator
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