Tcphardware accelerator IP

Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).
The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.

The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).

Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit

Generates bitmaps from graphics instructions as well as combining existing bitmaps on and off-screen using one of 256 Raster Operations. A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT) which lay the foundation for power hardware graphics primitive operations
Generates characters from compressed bitmaps using its FONT Bitmap Color Expansion Unit
Performs Alpha Blend operations of bitmaps with its Alpha Blend unit
Draws lines, polygons, circles using its hardware efficient & pixel accurate Bresenham Algorithm Line Drawing Unit

TCPHardware Accelerator IP