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Synopsys Memory IP

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Compare 329 IP from 5 vendors (1 - 10)
  • ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM9D 32-bit DSP Enhanced Processor core based on the ARCv2DSP ISA with CCM and XY Memory
  • ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
    • Dual 32x16 XMAC component supports up to two 32x16 MAC operations per instructions and supports all the 32x16 & dual 16x16 MAC instructions
    • Dual XMAC built in shifters and 80-bit accumulators allow pseudo floating-point operations to be performed which greatly expanded dynamic range
    • RAM configuration optimized for efficient area and power
    • Improved system efficiency with enhanced ARM® AMBA® AXI™/AHB™ bus bridges
    Block Diagram -- ARC EM11D Enhanced 32-bit processor core, ARCv2DSP ISA with Cache and XY Memory
  • Inline Memory Encryption (IME) Security Module - for DDR/LPDDR
    • Data confidentiality with independent cryptographic support for read & write channels
    • Standards compliant: NIST SP800-38E, IEEE Std. 1619-2018
    • FIPS 140-3 certification support
    • Per region protection (index or address based)
    Block Diagram -- Inline Memory Encryption (IME) Security Module - for DDR/LPDDR
  • Memory management unit (MMU) option for ARC HS5x and HS6x processors
    • Dual-issue, 64-bit processors for high-performance embedded applications
    • 52-bit physical and 64-bit virtual addressing
    • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
    • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
    Block Diagram -- Memory management unit (MMU) option for ARC HS5x and HS6x processors
  • L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
    • Dual-issue, 64-bit processors for high-performance embedded applications
    • 52-bit physical and 64-bit virtual addressing
    • Up to 5400 DMIPS and 11,088 CoreMark per core at 1.8 GHz on 16FFC (worst case conditions, single-core configuration
    • Multicore Processor versions with up to 12 CPU cores and up to 16 hardware accelerators
    Block Diagram -- L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors
  • Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
    • Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
    • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
    • Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
    Block Diagram -- Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
  • PUF Software Premium with key wrap and certification support
    • Most flexible and scalable PUF-based security solution for new and existing designs
    • Uses standard SRAM as a physical unclonable function (PUF) to create a hardware-based trust anchor which can be installed later in the supply chain, or even retrofitted on deployed devices
    • Offers key provisioning, secure key storage, symmetric and asymmetric key cryptography, and data encryption on the fly
    • Easy and collision-free identification of billions of devices (from various vendors)
  • UALink IP Solution
    • Lightweight, low latency IP solution for XPU to XPU interconnects optimized for AI workloads
    • Fully integrated IP solution for AI accelerators (XPUs), GPUs, and switches
    • Enables maximum throughput with up to 200Gbps per lane
    • Supports memory sharing capabilities to expand compute and memory resources from XPU to XPU
    Block Diagram -- UALink IP Solution
  • Optional extension of NPX6 NPU tensor operations to include floating-point support with BF16 or BF16+FP16
    • Scalable real-time AI / neural processor IP with up to 3,500 TOPS performance
    • Supports CNNs, transformers, including generative AI, recommender networks, RNNs/LSTMs, etc.
    • Industry leading power efficiency (up to 30 TOPS/W)
    • One 1K MAC core or 1-24 cores of an enhanced 4K MAC/core convolution accelerator
    Block Diagram -- Optional extension of NPX6 NPU tensor operations to include floating-point support with BF16 or BF16+FP16
  • Enhanced Neural Processing Unit providing 98,304 MACs/cycle of performance for AI applications
    • Scalable real-time AI / neural processor IP with up to 3,500 TOPS performance
    • Supports CNNs, transformers, including generative AI, recommender networks, RNNs/LSTMs, etc.
    • Industry leading power efficiency (up to 30 TOPS/W)
    • One 1K MAC core or 1-24 cores of an enhanced 4K MAC/core convolution accelerator
    Block Diagram -- Enhanced Neural Processing Unit providing 98,304 MACs/cycle of performance for AI applications
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