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Compare 1,099 IP from 60 vendors (1 - 10)
  • Vital signs healthcare sensor interface
    • Two Channels of multi-lead electrocardiogram (ECG)
    • Temperature sensor
    • Differential capacitive sensor channel
    Block Diagram -- Vital signs healthcare sensor interface
  • Configurable Multi-Scaler
    • The CMS-1 is a parameterized integration of the VSC-1 scaler core with other IP as needed for ABR and similar applications requiring simultaneous multiple output formats from a single input.
    • The CMS-1 is fully customizable through the use of Verilog parameters so that it may be tailored for use in various applications.
    • The number of simultaneously available outputs, scaler taps, phases, data path and coefficient precision are all configurable. A highly efficient implementation exploits the use of cascading as well as resource sharing in order to minimize implementation cost.
    Block Diagram -- Configurable Multi-Scaler
  • DiFi IP core
    • The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 targeting ASIC, and FPGA technologies.
    • The DiFi implementation builds on long-time experience designing IP cores for sending and receiving Radio IQ data over Ethernet networks, and delivers a flexible engine that is prepared for tight integration with software applications.
    Block Diagram -- DiFi IP core
  • ML-KEM Key Encapsulation IP Core
    • The KiviPQC™-KEM IP core is a hardware accelerator for post-quantum cryptographic operations.
    • It implements the Module Lattice-based Key Encapsulation Mechanism (ML-KEM), standardized by NIST in FIPS 203.
    • This mechanism realizes the appropriate procedures for securely exchanging a shared secret key between two parties that communicate over a public channel using a defined set of rules and parameters.
    Block Diagram -- ML-KEM Key Encapsulation IP Core
  • ONFI 3.0 Compatible I/O Buffer on TSMC CLN28HPL
    • High speed, source synchronous, bi-directional I/O buffer supporting the Open NAND Flash Interface (ONFI) 3.0 standard
    • Operation up to 200MHz DDR (400Mbps) performance with single load topology
    • Designed with core and 1.8V IO oxide devices
    • Built-in ODT (On-Die Termination)
  • DDR3/DDR3L Compatible I/O Buffer on TSMC CLN40G
    • High-Speed Bi-directional DDR3/DDR3L compatible I/O buffer
    • Operation up to 1066MHz DDR (2133Mbps) performance with single load topology
    • Designed with core and 1.8V IO oxide devices
    • Built-in ODT (On-Die Termination)
  • SpaceWire Verification IP
    • Compliant with ECSS E‐ST‐50‐12C Standard.
    • Supports speeds between 2 Mb/s and 400 Mb/s.
    • Supports sending packets of information from a source node to a specified destination node.
    • Supports full-duplex point-to-point serial data communication links.
    Block Diagram -- SpaceWire Verification IP
  • SpaceWire Synthesizable Transactor
    • Supports ECSS E‐ST‐50‐12C Standard
    • Supports speeds between 2 Mb/s and 400 Mb/s
    • Supports Full SpaceWire Functionality
    Block Diagram -- SpaceWire Synthesizable Transactor
  • 100G MAC/PCS Ultra Ethernet
    • The IP integrates MAC Layer, RS Sub-Layer and 100G PCS Base-R cores according to IEEE 802.3 standard to provide seamless connection between an application and serdes interfaces
    • 128-bit interface for TX and RX between MAC and the application Serdes interface – configurable to support PAM2 and PAM 4
    Block Diagram -- 100G MAC/PCS Ultra Ethernet
  • SpaceWire Verification IP
    • Available in UVM, System Verilog.
    • Compliant to Specification ECSS-E-ST-50-12 C rev 1.
    • Supports speeds between 2Mb/s to 400Mb/s
    • Supports full duplex Serial data communication links
    Block Diagram -- SpaceWire Verification IP
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