Sidense IP
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This IP is specially designed for anti-tamper protection which includes both current sense & voltage sense.
- Process: GSMC 0.18um 1P6M logic process
- Supply voltage: 2V~3.6V
- Voltage detectors & Current detectors
- Operating junction temperature: -40°C≤TJ≤+125°C
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802.11ax PHY Layer C Floating-Point Code IP for the STA mode
- This IP includes a recommendation-compliant 802.11ax PHY layer C floating-point code for the Station (STA) mode.
- The code is integrated into a simulation environment that allows the configuration of mandatory features and the performance evaluation in terms of frame error rate.
- It is designed to generate fixed-point sequences in order to accelerate the development of both C fixed-point code and HDL code for prototyping environments.
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Neuromorphic Processor IP
- In-Memory Compute: Efficient analog MACs for AI workloads
- Compact Footprint: 0.28 mm² including peripheral circuitry
- Wishbone Interface: Easy integration with standard digital buses
- Ready for Tapeout: Fully synthesized and foundry-compatible
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SD4.x UHSII
- Fully compliant with UHSII specification Ver. 4.x
- Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
- Supports data rates from 390Mbps to 1.56Gbps/ch
- RCLK frequency: 26 to 56MHz
- Built-in PLL and clock recovery
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3.3V Capable GPIO on TSMC 28nm RF HPC+
- The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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SOQPSK-TG Demodulator IP Core
- Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) is a type of QPSK/OQPSK modulation. SOQPSK-TG provides constant-envelope modulation with continuous phase.
- This minimizes spectral occupancy and improves resistance to interference and nonlinear amplification.
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Protocol controller IP for a CAN FD light responder node
- The FDLR_CAN is a CAN IP module that can be implemented in an ASIC, FPGA, and mixed-signal device.
- It supports CAN FD light responder communication according to ISO 11898-1:2024.
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Protocol controller IP for Classical CAN / CAN FD / CAN FD light commander and CAN XL
- The XS_CAN is a low gate count CAN IP module that can be realized as stand-alone device, as part of an SoC, as part of an ASIC, or on an FPGA.
- Safety Element out of Context (SEooC) according to ISO 26262-11:2018 Clause.Developed according to the automotive cybersecurity standard ISO 21434.
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Safety Enhanced GPNPU Processor IP
- A True SDV Solution
- Fully programmable – ideal for long product life cycles
- Scalable multicore solutions up to 864 TOPS
- Solutions for ADAS, IVI and ECU products