Sidense IP

The Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard and supports protocol extensions for Audio Video Bridging (AVB).
The Gigabit Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Media Independent Interface (GMII).

The silicon-proven Gigabit Ethernet IP core provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Media Independent Interface (GMII).
It also supports optional Reduced MII (RGMII), and Serial GMII (SGMII).

The 10/100 Ethernet Media Access Controller (MAC) IP core is compliant with the Ethernet IEEE 802.3-2002 standard and has passed interoperability testing at UNH-IOL.
The 10/100 Ethernet IP core provides an 10/100 Mbps Media Independent Interface (MII) and an optional processor interface; it also supports Reduced MII (RMII) and Serial MII (SMII).

The 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface between AHB/AXI Bus and the 10 Gigabit Media Independent Interface (XGMII) using a powerful 64-bit Scatter Gather DMA.
The 10 Gigabit Ethernet IP core is designed for applications such as integrated networking devices, host bus adapters, PCI-Express Ethernet controllers, and Ethernet adapter cards.

The Serial Lite III Streaming Intel® FPGA Intellectual Property (IP) core offers simple connectivity that enables rapid point-to-point data transfers across various transmission media, including printed circuit board (PCB), backplane, copper cabling, and fiber optics.

The Serial Lite II Intel® FPGA IP core provides a simple and lightweight way to move data from one point to another reliably at high speeds
It consists of a serial link of up to 16 bonded lanes with logic to provide a number of basic and optional link support functions
The Atlantic* interface is the primary access for delivering and receiving data.

The Siemens EDA AXI Verification IP Suite (Intel® FPGA Edition) provides bus functional models (BFMs) to simulate the behavior and to facilitate the verification of intellectual property (IP) that conforms to the Advanced Microcontroller Bus Architecture Advanced eXtensible Interface (AMBA* AXI) Protocol, with restrictions to simplify the application programming interface (API) for you.

The CMS-1 is a parameterized integration of the VSC-1 scaler core with other IP as needed for ABR and similar applications requiring simultaneous multiple output formats from a single input.
The CMS-1 is fully customizable through the use of Verilog parameters so that it may be tailored for use in various applications.
The number of simultaneously available outputs, scaler taps, phases, data path and coefficient precision are all configurable. A highly efficient implementation exploits the use of cascading as well as resource sharing in order to minimize implementation cost.

The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 targeting ASIC, and FPGA technologies.
The DiFi implementation builds on long-time experience designing IP cores for sending and receiving Radio IQ data over Ethernet networks, and delivers a flexible engine that is prepared for tight integration with software applications.