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Sidense IP

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Compare 1,088 IP from 56 vendors (1 - 10)
  • Vital signs healthcare sensor interface
    • Two Channels of multi-lead electrocardiogram (ECG)
    • Temperature sensor
    • Differential capacitive sensor channel
    Block Diagram -- Vital signs healthcare sensor interface
  • ComputeRAM
    • Available as a 18 kB macro in GlobalFoundries 22FDX process; - Memory Compiler and FinFET variants under development
    • Low power sleep mode with data retention
    • Built using proven foundry SRAM bit cells, fully CMOS, strictly obeys foundry DFM/DRC rules
    • Bit-accurate computation
    Block Diagram -- ComputeRAM
  • Complete USB Type-C Power Delivery PHY, RTL, and Software
    • USB PD 3.1 compliant.
    • 8 bit register interface for a low speed processor, or optional I2C interface.
    • Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
    Block Diagram -- Complete USB Type-C Power Delivery PHY, RTL, and Software
  • Universal NVM Express Controller (UNEX)
    • Compliant to NVM Express 1.1
    • Support for configurable number of IO Queues
    • Support for configurable Queue depth
    Block Diagram -- Universal NVM Express Controller (UNEX)
  • Open RAN Platform for Base Station and Radio
    • Fully configurable comprehensive IP platform for 5G NR and multi-mode RAT addressing both Basestation and Radio Open RAN use cases
    Block Diagram -- Open RAN Platform for Base Station and Radio
  • Bluetooth Dual Mode (Classic & BLE ) v5.3 Protocol Software Stack and Profiles IP
    • Bluetooth SIG Qualified, Production Proven IP
    • Proven Interoperability
    • Low MIPS and Memory Footprint for Stack & Profiles
    • Platform and Operating Systems (OS) agnostic and is designed for Easy Portability
    Block Diagram -- Bluetooth Dual Mode (Classic & BLE ) v5.3 Protocol Software Stack and Profiles IP
  • High Performance DDR5/4/3 Memory Controller
    • Compliant with AXI4 Specification
    • Compliant with DFI 3.1 Specification
    • Compliant with JEDEC DDR3, DDR3L, DDR4 and DDR5 standards
    • Supports 64, 32, 16 and 8 bit Memory SDRAM for DDR3L, DDR4 and DDR5
    Block Diagram -- High Performance DDR5/4/3 Memory Controller
  • RapidIO Controller with V4.1 Support
    • Compliant to RapidIO Specifications revision 4.1
    • Compliant with RapidIO Error Management
    • Extension specification, Revision 4.1
    • Implements Logical, Transport and Physical layers functions
    Block Diagram -- RapidIO Controller with V4.1 Support
  • Bluetooth 5.4 LE Host
    • Bluetooth SIG Qualified for BLE 5.4
    • Production proven IP, extensively tested, commercially shipping
    • Host Protocol Stack and GATT Profile Features
    • • Full BLE 5.4 feature set including: EAD and host support for PAwR
    Block Diagram -- Bluetooth 5.4 LE Host
  • SD4.1 UHS- II PHY IP
    • SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
    • 16bit interface to Link layer
    • Supports both Full Duplex mode and Half Duplex mode
    Block Diagram -- SD4.1 UHS- II PHY IP
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