Security Processor IP
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107
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RT-650 DPA-Resistant Hardware Root of Trust Security Processor for Govt/Aero/Defense FIPS-140
- Secure co-processor
- Main processor agnostic
- Standard secure applications
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RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Superior Security
- Enhanced Flexibility
- Security Models
- Cryptographic Accelerators
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RT-660-FPGA DPA-Resistant Hardware Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140
- Superior Security
- Enhanced Flexibility
- Security Models
- Cryptographic Accelerators
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RT-660 DPA & Fault Injection Resistant Hardware Root of Trust Security Processor for Govt/Aero/Defense FIPS-140
- Superior Security
- Enhanced Flexibility
- Security Models
- Cryptographic Accelerators
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RT-630 Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Superior Security
- Enhanced Flexibility
- Security Models
- Cryptographic Accelerators
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IEEE 802.1ae (MACsec) Security Processor
- Small size combined with high performance:
- Self-contained, uses two external memories for key storage and statistic counters
- Very low latency
- Back-to-back packet processing
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IEEE 802.1ae (MACsec) 100G Security Processor with Avalon-ST Interface
- Small size combined with high performance
- Self-contained
- Very low latency
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IPsec Security Processor
- Support for IPv4 and IPv6 packets
- Support for the IPsec ESP and AH protocols:
- Support for IPsec ESP encryption algorithms per RFC 4835:
- Support for IPsec ESP (and AH for –AH option) authentication algorithms per RFC 4835:
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Performance-efficient, ultra-low power, compact ARC SEM security processors help protect against logical, hardware, physical and side-channel attacks
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
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Compact Processor for Security
- Secure MPU against memory tampering
- Shields against side-channel attack
- Secure debug for multi-party software development
- Flexible configurations and run-time control
