Security processor IP

Performance-, power- and area-efficient security processors for embedded applications
Secure privilege mode orthogonal to kernel/user mode
Enhanced secure MPU with context ID for secure or normal operation
Up to 16 configurable protected regions and per region scrambling capability

Performance-, power- and area-efficient security processors for embedded applications
Secure privilege mode orthogonal to kernel/user mode
Enhanced secure MPU with context ID for secure or normal operation
Up to 16 configurable protected regions and per region scrambling capability

ASIL D compliant dual-core, lockstep safety processor supports ISO 26262 automotive safety standards and provides advanced security to protect against evolving threats
Secure privilege mode orthogonal to kernel/user mode
Integrated self-checking safety monitor capable of time diversity
Uniform instruction timing and timing/ power randomization for side channel resistance

Small size combined with high performance:
Self-contained, uses two external memories for key storage and statistic counters
Very low latency
Back-to-back packet processing

Support for IPv4 and IPv6 packets
Support for the IPsec ESP and AH protocols:
Support for IPsec ESP encryption algorithms per RFC 4835:
Support for IPsec ESP (and AH for –AH option) authentication algorithms per RFC 4835:

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

The automotive-grade CryptoManager RT-7xx v3 Root of Trust family is the next generation of fully programmable ISO 26262 and ISO 21434 compliant hardware security modules offering Quantum Safe security by design for secure automotive applications.
The CryptoManager RT-7xx family protects against a wide range of hardware and software attacks through state-of-the-art side channel attack countermeasures and anti-tamper and security techniques.

The RT-64x Embedded Hardware Security Module (Root of Trust) family are fully programmable, ISO 26262 ASIL-B hardware security cores offering security by design for automotive applications.
They protect against a wide range of failures such as permanent, transient and latent faults and hardware and software attacks with state-of-the-art anti-tamper and security techniques.