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Secure Execution Processor IP

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  • Secure Execution Processor
    • The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data.
    • It uses two or more cryptographically separated execution contexts for a high degree of security during code execution and for data storage and transfer to and from the processor.
    Block Diagram -- Secure Execution Processor
  • Secure Execution Processor
    • Two cryptographically isolated secure execution contexts
    • Cryptographic primitives agnostic
    • Lowest overhead implementation with single Keccak (SHA3) core
    Block Diagram -- Secure Execution Processor
  • Low power 32-bit processor with secure execution capability
    • Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
    • Pipeline: 3-stage;
    • General register: 16 32-bit GPRs;
    • Bus interface: Tri-bus (instruction bus + data bus + system bus) ;
    Block Diagram -- Low power 32-bit processor with secure execution capability
  • Ultra-low power 32-bit processor with secure execution capability
    • Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
    • Pipeline: 2-stage;
    • General register: 16 32-bit GPRs;
    • Bus interface: Dual bus (instruction bus + data bus);
    Block Diagram -- Ultra-low power 32-bit processor with secure execution capability
  • Ultra-low power processor with RISC-V architecture possessing secure execution capability
    • Instruction set: T-Head ISA (compatible with RV32EMC/RV32EC/RV32IMC);
    • Pipeline: 2-stage;
    • Permission mode: Optional M state or M+U state;
    • General register: 16 32-bit GPRs;
    Block Diagram -- Ultra-low power processor with RISC-V architecture possessing secure execution capability
  • ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
    • Performance-, power- and area-efficient security processors for embedded applications
    • Secure privilege mode orthogonal to kernel/user mode
    • Enhanced secure MPU with context ID for secure or normal operation
    • Up to 16 configurable protected regions and per region scrambling capability
    Block Diagram -- ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
  • ARC SEM110 Security Processor for Low Power Embedded Applications
    • Performance-, power- and area-efficient security processors for embedded applications
    • Secure privilege mode orthogonal to kernel/user mode
    • Enhanced secure MPU with context ID for secure or normal operation
    • Up to 16 configurable protected regions and per region scrambling capability
    Block Diagram -- ARC SEM110 Security Processor for Low Power Embedded Applications
  • ARC SEM130FS Safety and Security Processor
    • ASIL D compliant dual-core, lockstep safety processor supports ISO 26262 automotive safety standards and provides advanced security to protect against evolving threats
    • Secure privilege mode orthogonal to kernel/user mode
    • Integrated self-checking safety monitor capable of time diversity
    • Uniform instruction timing and timing/ power randomization for side channel resistance
    Block Diagram -- ARC SEM130FS Safety and Security Processor
  • tRoot V500 Hardware Secure Module
    • Complete hardware secure modules with Root of Trust give SoCs a unique, tamper-proof identity
    • Enable secure services deployment
    • Provide a Trusted Execution Environment to create, provision, store and manage keys
    • Full hardware key protection
    Block Diagram -- tRoot V500 Hardware Secure Module
  • tRoot Vx Hardware Secure Modules
    • The Synopsys tRoot Vx HSMs include a highly secure hardware Root of Trust that enables devices to boot securely and permits encryption and decryption of sensitive data allowing it to be stored in non-secure devices or memory. It provides a completely secure environment in a non-secure system from which applications can execute secure cryptographic services.
    • The tRoot Vx HSMs secure SoCs by using unique code protection mechanisms that provide run-time tamper detection and response. Code privacy protection is achieved without the added cost of dedicated secure memory. This unique feature reduces system complexity and cost by allowing the tRoot Vx HSM’s firmware to reside in any non-secure memory space.
    • Commonly, tRoot Vx programs reside in shared system DDR memory. Due to the confidentiality and integrity provisions of the secure instruction controller, this memory is effectively private to the HSM and impervious to attempts to modify it originating in other subsystems in the chip, or from outside. The tRoot Vx HSM’s ROM-less architecture can support system design changes at any time without risk of exposing the system memory to threats and without additional engineering development cost. To minimize the number of attack vectors, tRoot Vx HSMs use a simple interface with a limited set of interactions with the host processor.
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