SPI Controller IP
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142
IP
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44
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10)
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SPI Controller
- The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.
- Through registers mapped into APB address space the core can be configured to work either as a master or a slave.
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SPI Controller IP- Master/ Slave, Parameterized FIFO, Avalon Bus
- The Digital Blocks DB-SPI-MS-AVLN is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers.
- The DB-SPI-MS contains an Avalon Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.
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Octal SPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) and DMA Support
- Full Octal SPI Master Functionality
- Fast frequency support (Up to 133MHz)
- Compliant to the SPI de-facto standard
- Single, dual, quad, and octal serial data lines
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Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
- The DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave Controller. The DB-eSPI-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external eSPI or SPI Master/Slave devices.
- The DB-eSPI-SPI-MS contains both eSPI and SPI Master and Slave functions.
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Dolphin Quad SPI Controller
- Dolphin Quad-SPI Controller supports:
- + Master only operation
- + Slave only operation
- + Master and slave operation
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Dolphin Octal SPI Controller
- Dolphin Octal-SPI Controller supports:
- - Master only operation
- - Slave only operation
- - Master and slave operation
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AHB Quad SPI Controller with Execute in Place (XIP)
- The Quad Serial Peripheral Interface module either controls a serial data link as a master component, or reacts to a serial data link as a slave component.
- The IPC-QSPI-AHB bus controller can be configured under software control to be a master component or slave component device. Reading and writing the core is done on the AMBA AHB bus interface.
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AHB Octal SPI Controller with PSRAM and XIP Support
- The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an industry-standard FLASH or PSRAM memory device.
- In Software Mode, an AHB Master may access the register interface of the Controller to implement a wide range of protocol variants and/or commands on the SPI bus.
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SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex).
- The DB-SPI-M contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Slave devices.
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Quad SPI Controller
- Configurable SPI modes
- Supports programmable SPI clocking modes
- Programmable interrupt on SPI-done
