Spi controller IP

The Digital Blocks DB-SPI-MS-AVLN is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers.
The DB-SPI-MS contains an Avalon Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.

The DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave Controller. The DB-eSPI-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external eSPI or SPI Master/Slave devices.
The DB-eSPI-SPI-MS contains both eSPI and SPI Master and Slave functions.

The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex).
The DB-SPI-M contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Slave devices.

The DB-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.
The DB-SPI-MS contains Transmit/Receive FIFOs and Finite State Machine control with status & interrupt capability to fully off-load from the microprocessor the transfer of data over the SPI Bus. Optionally, the user can transfer transmitted or received data from the SPI Bus to user memory via an optional DMA Controller.