Spi controller IP

The SPI controller support master/slave operation over the single-lane, dual-lane,quad-lane and half duplex singlelane protocols
Programmable clock polarity and phase (CPOL/CPHA)
Configurable MSB First or LSB First
Master/Slave mode configurable frequency (FPCLK/2 max)
SPI bus busy status flag

The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.
Through registers mapped into APB address space the core can be configured to work either as a master or a slave.

The Digital Blocks DB-SPI-MS-AVLN is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers.
The DB-SPI-MS contains an Avalon Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.

The DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave Controller. The DB-eSPI-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external eSPI or SPI Master/Slave devices.
The DB-eSPI-SPI-MS contains both eSPI and SPI Master and Slave functions.

Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations.
The Quad SPI IP either controls a serial data link as a master, or reacts to a serial data link as a slave.
The core operates in various data modes from 4 bits to 32 bits.
The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus.

The Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with reduced read latency, including support for Octal DDR protocol with DQS for Octal SPI devices.

The Quad Serial Peripheral Interface module either controls a serial data link as a master component, or reacts to a serial data link as a slave component.
The IPC-QSPI-AHB bus controller can be configured under software control to be a master component or slave component device. Reading and writing the core is done on the AMBA AHB bus interface.

The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an industry-standard FLASH or PSRAM memory device.
In Software Mode, an AHB Master may access the register interface of the Controller to implement a wide range of protocol variants and/or commands on the SPI bus.

The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex).
The DB-SPI-M contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Slave devices.