Serdes phy on tsmc 12ffc IP

Compare 15 IP from 4 vendors (1 - 10)

Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
- Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
- Compact form factor – 0.116 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
PCI Express Gen3 SERDES PHY on TSMC CLN40G
- Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
- Compact form factor – 0.107 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 6.9 mW/Gbps including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
Programmable Low Power SERDES on TSMC CLN40G
- Programmable SERDES analog front end that supports 1 to 11+ Gbps standard serial protocols
- Compact form factor – 0.104 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 5.8 mW/Gbps including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
Programmable Low Power SERDES on TSMC CLN28HPL
- Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
- Compact form factor – 0.095 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 5.6 mW/Gbps including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
- Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Support for Ethernet protocols and Automotive Grade 2
- Compact form factor – 0.34 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
- Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Support for Ethernet protocols and Automotive Grade 2
- Compact form factor – 0.34 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
Low Power PCIe3/SATA3 Gen3 PHY on TSMC CLN28HPC+
- Industry leading low power PMA macro – 56mW per lane at 8Gbps (7mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.2 mm2 total active area per lane
- Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
- Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 1- tap DFE
Low Power PCIe Gen3 PHY on TSMC CLN16FFC
- Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.133 mm2 total active area per lane
- Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
- Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 5- tap DFE
Low Power PCIe Gen3 PHY on TSMC CLN12FFC
- Industry leading low power PMA macro – 39mW per lane at 8Gbps (4.88mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.133 mm2 total active area per lane
- Supported protocols include: PCIe Gen3/2/1, SATA3/2/1, XAUI/RXAUI, SGMII
- Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and 5- tap DFE
Low Power 1-22G PCIe Gen4 / SAS4 PHY on TSMC CLN16FFC
- Industry leading low power PMA macro – 184mW per lane at 22.5Gbps (8.2mW/Gbps) and 108mW per lane at 16Gbps (6.75mW/Gbps), inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.145 mm2 total active area per lane
- Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
- Multi-orientation macros of 4, 8 and 16 lane SERDES are available for most common metal stacks

SERDES PHY on TSMC 12FFC IP