IP Catalog > SERDES PHY On TSMC 12FFC

SERDES PHY on TSMC 12FFC IP

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Compare 10 IP from 4 vendors (1 - 10)
  • PHY for PCIe 5.0 and CXL for TSMC 7nm FinFet
    • High-performance PHY for data center applications
    • Low-latency, long-reach, and low-power modes
    • Wide range of protocols that support networking, storage, and computing applications
    • Multi-protocol support for application flexibility
  • PHY for PCIe 5.0 and CXL for TSMC 5nm FinFet
    • High-performance PHY for data center applications
    • Low-latency, long-reach, and low-power modes
    • Wide range of protocols that support networking, storage, and computing applications
    • Multi-protocol support for application flexibility
  • USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP
    • Support half rate mode (5Gbps) and full rate mode (10Gbps)
    • Tolerate max +/-7000ppm input frequency offset
    • 32bit/40bit selectable parallel data bus
    • Programmable transmit amplitude
    Block Diagram -- USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP
  • INNOLINK-B PHY
    • Support both Die2Die and Chip2Chip application
    • GDDR6 like interface with IO voltage is core power supply (0.8V for TSMC 12nm)
    • 24Gbps for maximum IO speed
    • Default 16bit DQ Tx+ 16bit DQ Rx per module, module number can be 1/2/4/8/16 or more
  • 40G Ultralink D2D PHY for TSMC 7nm
    • Flexible data rate from 20Gbps to 40Gbps
    • Single-ended NRZ signaling scheme
    • BIST features ensure Known Good Die (KGD)
    • Sideband for link management
  • 40G Ultralink D2D PHY for TSMC 5nm
    • Flexible data rate from 20Gbps to 40Gbps
    • Single-ended NRZ signaling scheme
    • BIST features ensure Known Good Die (KGD)
    • Sideband for link management
  • 40G Ultralink D2D PHY for TSMC 3nm
    • Flexible data rate from 20Gbps to 40Gbps
    • Single-ended NRZ signaling scheme
    • BIST features ensure Known Good Die (KGD)
  • 112G Ethernet PHY in TSMC (N7, N5, N3P)
    • Optimized for performance, power, and area
    • Includes one, two, or four full-duplex PAM-4 transceivers (transmit and receive functions)
    • Supports IEEE and OIF standards: IEEE 802.3ck, CEI-112G
    • Includes auto-negotiation and link training capabilities – IEEE 802.3 clause 73
  • 224G Ethernet PHY in TSMC (N3E)
    • Optimized for performance, power, and area
    • Includes one, two, or four full-duplex PAM-4/6 transceivers (transmit and receive functions)
    • Supports IEEE and OIF-CEI-224G standards
    • Includes auto-negotiation and link training capabilities
  • GDDR6 PHY for TSMC
    • Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
    • Memory controller interface uses DFI 5.0-like standard with extensions for GDDR6
    • Internal and external datapath loop-back modes
    • Per-bit DFE, CTLE, and FFE equalization
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