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SD 4.1 IP

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  • SD 4.1 Hardware Validation Platform
    • Designed to be cost-effective and Linux based, this SD 4.1 hardware validation platform (HVP) consists of Arasan’s SD4.0 IP mapped into FPGA’s, offering full speed physical connectivity to a complementary SoC host or memory card device.
    Block Diagram -- SD 4.1 Hardware Validation Platform
  • SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
    • The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies.
    • SD 4.1 Host Controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    Block Diagram -- SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
  • SD 4.1 Host Controller Software Stack
    • This is a production-ready stack for Arasan’s eMMC Host Controller IP that is used to connect to SD, SDIO, or eMMC devices.
    • The SD4/SDIO4/eMMC 4.5.1 Stack can also be used for validating a device during its development and integration life cycles thereby helping designers to reduce the time to market for their product.
    Block Diagram -- SD 4.1 Host Controller Software Stack
  • SD 4.1 Device Controller IP
    • Fully compliant core with proven silicon
    • Compliant with SD Specification Part E SD Specification 4.0
    • Transfers up to 300 MB/s (UHS156)
    • Supports Asynchronous Interrupt to Host controller
    • Enhanced power management using new Power
    Block Diagram -- SD 4.1 Device Controller IP
  • SD 4.1 eMMC 5.1 Dual Host Controller IP
    • The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
    • The SD 4.1 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 4.1 / eMMC5.1 Host IP.
    • eMMC 5.1 is backward compatible to the previous versions.
    •  
    Block Diagram -- SD 4.1 eMMC 5.1 Dual Host Controller IP
  • UHS-II PHY Core IP
    • The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries.
    • It uses sub-LVDS signaling consisting of one pair each for transmit, receive, and an additional reference clock. This low-pin interface has reduced power consumption and low EMI.
    • To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed.
    Block Diagram -- UHS-II PHY Core IP
  • SD4.1 UHS- II PHY IP
    • SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
    • 16bit interface to Link layer
    • Supports both Full Duplex mode and Half Duplex mode
    Block Diagram -- SD4.1 UHS- II PHY IP
  • SD/eMMC Lite Host Controller IP
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Lite Host Controller IP
  • SD/eMMC Host Controller IP
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Host Controller IP
  • SD/eMMC Crypto Host Controller
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Crypto Host Controller
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