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SD 4.1 IP

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Search (13)
Compare 13 IP from 6 vendors (1 - 10)
  • SD 4.1 UHS-II PHY for TSMC 12nm FF
    • Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II Specification Volume 1: System and Protocol”
  • SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
    • Fully compliant core with proven silicon
    • Premier direct support from Arasan IP core designers
    • Easy-to-use industry standard test environment
  • Block Diagram -- SD 4.1 SDIO 4.1 Host Controller IP
  • SD4.1 UHS- II PHY IP
    • SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
    • 16bit interface to Link layer
    • Supports both Full Duplex mode and Half Duplex mode
    Block Diagram -- SD4.1 UHS- II PHY IP
  • SD/eMMC Lite Host Controller IP
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Lite Host Controller IP
  • SD/eMMC Host Controller IP
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Host Controller IP
  • SD/eMMC Crypto Host Controller
    • Compliant with the SD 6.0, SDIO 4.10 and eMMC 5.1 specifications and earlier versions
    • Supports advanced eMMC features including HS400 mode and built-in CQE with priority sensitive scheduling algorithm for high performance
    • Low power features with power gating and multi-power rails
    • Supports the host controller interface (HCI) specification for SD ensuring the usability of standard software drivers with support for SDMA, ADMA2 and ADMA3 modes
    Block Diagram -- SD/eMMC Crypto Host Controller
  • Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
    • Compliant with SD HCI specification
    • CQE capable of reordering task execution based on priority
    • Data prefetching for back to back tasks—further improves random IOPS
    • Low-power features with power gating and multi-power rails
  • SDIO UHS II Verification IP
    • Supports SD specification UHS-II Adddendum version 2.00 compliant.
    • Supports Part E1 SDIO specification version 4.10.
    • Supports SD specification physical layer version 4.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0(Draft).
    • Supports bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes.
    Block Diagram -- SDIO UHS II Verification IP
  • SDIO Host Controller IIP
    • Compliant with SD Host Controller Specification version 4.0
    • Compliant with Part E1 SDIO specification 4.10
    • Supports SDMA, ADMA2 and ADMA3 modes
    • Supports 1-bit, 4-bit bus mode and SPI Bus mode
    Block Diagram -- SDIO Host Controller IIP
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