SD 4.1 IP

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Compare 10 IP from 6 vendors (1 - 10)
  • Block Diagram -- SD 4.1 SDIO 4.1 Host Controller IP
  • SD 4.1 / SDIO 4.0 / eMMC 5.1 Host Controller
    • Fully compliant core with proven silicon
    • Premier direct support from Arasan IP core designers
    • Easy-to-use industry standard test environment
  • SD 4.1 UHS-II PHY for TSMC 12nm FF
    • Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II Specification Volume 1: System and Protocol”
  • Low-power SD/eMMC host controller IP provides advanced high-performance 32- and 64-bit AXI interface to the SoC
    • Compliant with SD HCI specification
    • CQE capable of reordering task execution based on priority
    • Data prefetching for back to back tasks—further improves random IOPS
    • Low-power features with power gating and multi-power rails
  • SDIO Device IP
    • Compliant with Part E1 SD Specification version 4.10 and earlier versions
    • Supports all commands/response types
    • Supports 1-bit, 4-bit ,8 bit SD bus mode and SPI Bus mode
    • Supports CRC7 checking/generation for command/response
  • SDIO Host IP
    • Compliant with SD Host Controller Specification version 6.0
    • Compliant with SDIO Physical Specification version 6.10
    • Compliant with Part E1 SDIO specification 4.10
    • Supports SDMA, ADMA2 and ADMA3 modes
  • SD4.1 UHS- II PHY IP
    • SD 4.1 compliant SDHC/SDXC UHS-II Physical Layer for Host
    • 16bit interface to Link layer
    • Supports both Full Duplex mode and Half Duplex mode
    Block Diagram -- SD4.1 UHS- II PHY IP
  • HD H.264 decoder
    • Fully compliant with ITU-T Recommendation H.264 | ISO/IEC 14496-10 AVC
    • Support Main Profile up to Level 4.1 with the maximum bitrate at 50Mps
    • Decode up to 720p @ 60fps, 1080HD @ 30fps
    • Support complete Main Profile H.264 tools
  • UHS II
    • The type of connection topology supported by UHS
    Block Diagram -- UHS II
  • UHS-II Device Controller
    • Compliance with Part 1 UHS-II Addendum Version 1.02
    • Compliance with Part A2 SD Host controller specification version 4.10 & Part1 Physical layer specification version 4.20
    • Programmable 1 or 2 Data lane Configuration
    • Supports all type of packets
    Block Diagram -- UHS-II Device Controller
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Semiconductor IP