IP Catalog > SATA PCI Express Host Bus Adapter

SATA PCI Express Host Bus Adapter IP

Filter
Filter

Login required.

Sign in

Search (15)
Compare 15 IP from 7 vendors (1 - 10)
  • IDE Security IP Modules for PCI Express 7.0
    • Full support of PCI Express 7.0 (64GT/s) IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP/FLIT packet-based interface
    • FLIT mode support
    • Support for PCIe 7.0, 6.0, 5.0, 4.0 and 3.1 data rates
    Block Diagram -- IDE Security IP Modules for PCI Express 7.0
  • Lancero Scatter-Gather DMA Engine for PCI Express
    • PCIe I/O performance: 200 MB/s x1 Gen 1 up to 3360 MB/s x8 Gen 2
    • Easily connect logic and high-speed I/O peripherals to PCI Express
    • Target Bridge supports Avalon Memory Mapped custom logic
    • SGDMA Engine supports Avalon Streaming burst access devices
    Block Diagram -- Lancero Scatter-Gather DMA Engine for PCI Express
  • ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
    • Compliant with PCI Express IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
    Block Diagram -- ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
  • PCIe 6.0 Integrity and Data Encryption Security Module
    • Compliant with PCI Express IDE specification
    • Support for TDISP
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • FLIT mode support
    Block Diagram -- PCIe 6.0 Integrity and Data Encryption Security Module
  • PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
    • Full support of PCI Express 7.0 (64GT/s) IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
  • ASIL B Ready PCIe 5.0 Integrity and Data Encryption Security Module
    • Compliant with PCI Express IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
    Block Diagram -- ASIL B Ready PCIe 5.0 Integrity and Data Encryption Security Module
  • PCIe 5.0 Integrity and Data Encryption Security Module
    • Compliant with PCI Express IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
    Block Diagram -- PCIe 5.0 Integrity and Data Encryption Security Module
  • NVMe IP core -- Directly connect PCIe SSD without external memory
    • NVMe IP core is standalone NVMe Host Controller with built-in optimized PCIe Bridge and Internal Memory Buffer, designed to handle NVMe Protocol without need CPU/OS and External DDR memory.
    • It’s recommended for the application which requires high performance, high storage capacity, very compact system size and easily to support multiple NVMe SSDs.
    Block Diagram -- NVMe IP core -- Directly connect PCIe SSD without external memory
  • NVMe 2.0 Verification IP
    • Compliant with the NVMe 2, 1.4, 1.3, 1.2 specification.
    • Compliant with PCI Express Specifications 6.0 v0.7(64GT/s), 5.0 v1.0(32GT/s), 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
    • Compliant with PIPE Specification 6.0,5.1, 4.4.1.
    • NVMe on top of Low Power, CXS, CPI, CXL, CXL Security, PCIe Gen6/5/4/3 management
    Block Diagram -- NVMe 2.0 Verification IP
  • CXL 2.0 Controller
    • Internal data path size automatically scales up or down (256, 512 bits) based on max. link speed and width for reduced gate count and optimal throughput
    • Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
    • Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
    Block Diagram -- CXL 2.0 Controller
×
Semiconductor IP