SATA PCI Express Host Bus Adapter IP

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Compare 19 IP from 11 vendors (1 - 10)
  • PCIe - PCI Express Controller
    • The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.
    • It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.
    Block Diagram -- PCIe - PCI Express Controller
  • Multichannel DMA Intel FPGA IP for PCI Express*
    • The Multichannel DMA IP for PCI Express provides high efficiency, speed, and configuration flexibility to support various applications from HPC, cloud, networking, to embedded
    • With support for up to 2048 channels and Linux-based PCIe drivers provided, this low latency, low resource utilization solution is essential in handling movements of large volumes of data to optimize system performance.
    Block Diagram -- Multichannel DMA Intel FPGA IP for PCI Express*
  • IDE Security IP Modules for PCI Express 7.0
    • Full support of PCI Express 7.0 (64GT/s) IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP/FLIT packet-based interface
    • FLIT mode support
    • Support for PCIe 7.0, 6.0, 5.0, 4.0 and 3.1 data rates
    Block Diagram -- IDE Security IP Modules for PCI Express 7.0
  • Lancero Scatter-Gather DMA Engine for PCI Express
    • PCIe I/O performance: 200 MB/s x1 Gen 1 up to 3360 MB/s x8 Gen 2
    • Easily connect logic and high-speed I/O peripherals to PCI Express
    • Target Bridge supports Avalon Memory Mapped custom logic
    • SGDMA Engine supports Avalon Streaming burst access devices
    Block Diagram -- Lancero Scatter-Gather DMA Engine for PCI Express
  • PCI Express PIPE PHY Transceiver
    • Supports 2.5Gb/s serial data rate
    • Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
    • Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
    • Data and clock recovery from serial stream on the PCI Express bus
    Block Diagram -- PCI Express PIPE PHY Transceiver
  • ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
    • Compliant with PCI Express IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
    Block Diagram -- ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
  • PCIe 6.0 Integrity and Data Encryption Security Module
    • Compliant with PCI Express IDE specification
    • Support for TDISP
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • FLIT mode support
    Block Diagram -- PCIe 6.0 Integrity and Data Encryption Security Module
  • PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
    • Full support of PCI Express 7.0 (64GT/s) IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
  • ASIL B Ready PCIe 5.0 Integrity and Data Encryption Security Module
    • Compliant with PCI Express IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
    Block Diagram -- ASIL B Ready PCIe 5.0 Integrity and Data Encryption Security Module
  • PCIe 5.0 Integrity and Data Encryption Security Module
    • Compliant with PCI Express IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
    Block Diagram -- PCIe 5.0 Integrity and Data Encryption Security Module
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