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SATA 6G IP

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Compare 123 IP from 8 vendors (1 - 10)
  • SATA 6G PHY in GF (40nm, 28nm)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • SATA 6G Host Controller IP
    • Compliant with SATA/eSATA v3.3 and SATA PIPE v4.3 specifications
    • Memory data protection and memory address parity protection
    • Hardware support for native nommand queuing (NCQ)
    • End-to-end parity data path protection
  • SATA 6G Device Controller IP
    • Compliant with SATA/eSATA v3.3 and SATA PIPE v4.3 specifications
    • Memory data protection and memory address parity protection
    • Hardware support for native nommand queuing (NCQ)
    • End-to-end parity data path protection
  • SATA 6G PHY in UMC (40nm, 28nm, 22nm)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • SATA 6G PHY in TSMC (40nm, 28nm, 16nm, 12nm, N7)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • SATA 6G PHY in SMIC (40nm, 28nm)
    • Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
    • AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
    • AMBA 4 AXI and ACE-Lite bus interfaces
    • Memory data protection and memory address parity protection
  • SATA 6G PHY
    • ? 6-Gbps transmission rate through standard SATA cable
    • ? Spread-spectrum clock (SSC) generation and absorption
    • ? Programmable down-spread (+4,980 ppm through -4,980 ppm)
    • ? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY
  • Multiprotocol 10G PHY, TSMC N7 x2, North/South (vertical) poly orientation
    • Supports 1.25 Gbps to 10 Gbps data rates
    • Supports PCI Express 3.1, SATA 6G, SGMII
    • Supports x1 to x16 macro configurations
    Block Diagram -- Multiprotocol 10G PHY, TSMC N7 x2, North/South (vertical) poly orientation
  • 10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
    • Supports 1.25 Gbps to 10 Gbps data rates
    • Supports PCI Express 3.1, SATA 6G, SGMII
    • Supports x1 to x16 macro configurations
    Block Diagram -- 10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
  • 10G PHY for PCIe 3.0, TSMC 7FF x4, North/South (vertical) poly orientation
    • Supports 1.25 Gbps to 10 Gbps data rates
    • Supports PCI Express 3.1, SATA 6G, SGMII
    • Supports x1 to x16 macro configurations
    Block Diagram -- 10G PHY for PCIe 3.0, TSMC 7FF x4, North/South (vertical) poly orientation
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