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Regular eXpression Processor IP

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Compare 19 IP from 12 vendors (1 - 10)
  • Block Diagram -- VME System Controller with AXI4 user interface and 2eSST support
  • Process Monitor
    •  Monitors process of Regular threshold voltage (RVT), Thick oxide (TD), High threshold voltage (HVT) devices. It monitors the process of Resistor and Capacitor as well.
    •  Digital supply Voltage range is from 0.9V to 1.1V, typical voltage is 1V.
    Block Diagram -- Process Monitor
  • DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
    • Performance of Greater than 100MHz (200 DDR)
    • Interfaces to JEDEC Standard DDR SDRAMs
    • Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits
    • Supports up to 8 External Memory Banks
    Block Diagram -- DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
  • DDR SDRAM Controller - Non-Pipelined
    • Performance of Greater than 133MHz (266 DDR)
    • Interfaces to JEDEC Standard DDR SDRAMs
    • Supports DDR SDRAM Data Widths of 16, 32 and 64 bits
    • Supports up to 8 External Memory Banks
    Block Diagram -- DDR SDRAM Controller - Non-Pipelined
  • Rx MPEG TS Interface
    • De-buffering and de-jittering MPEG-TS packets
    • Single clock (125MHz or higher)
    • Supports CBR input streams only (a BYPASS mode is available for VBR input streams)
    • Supports 188, 204 or 208 bytes packet input
    Block Diagram -- Rx MPEG TS Interface
  • SGMII SerDes
    • Separate PLLs for Tx and Rx
    • Compatible with arbitrary numbers of parallel lanes
    • 10bit datapath for TX and RX
    • Flexible driver and receiver circuits compatible with LVDS, 4b current programming
    Block Diagram -- SGMII SerDes
  • Non-Power-of-Two FFT
    • Sample Rates: Very high clock speeds
    • FFT size: any size set of transforms (chosen at run-time) factorable into bases up to ~10
    Block Diagram -- Non-Power-of-Two FFT
  • CCSDS (8160,7136) LDPC Decoder
    • CCSDS compatible
    • Rate 223/255 (8160,7136)
    • Includes ping-pong input and output memories
    • Up to 488 MHz internal clock
    Block Diagram -- CCSDS (8160,7136) LDPC Decoder
  • Low Power Multi-Rate SerDes
    • Data rates of <200Mb/s to >8Gb/s
    • Compatible with SGMII, SATA, FibreChannel, JESD 204, V-by-One
    Block Diagram -- Low Power Multi-Rate SerDes
  • Lancero Scatter-Gather DMA Engine for PCI Express
    • PCIe I/O performance: 200 MB/s x1 Gen 1 up to 3360 MB/s x8 Gen 2
    • Easily connect logic and high-speed I/O peripherals to PCI Express
    • Target Bridge supports Avalon Memory Mapped custom logic
    • SGDMA Engine supports Avalon Streaming burst access devices
    Block Diagram -- Lancero Scatter-Gather DMA Engine for PCI Express
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Semiconductor IP