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PQC IP

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Compare 23 IP from 11 vendors (1 - 10)
  • Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
    • PQCryptoLib-Emebedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
    • With its design focused on ultra-small memory footprint, PQCryptoLib-Embedded solutions have been specically designed for embedded systems, microcontrollers and memory-constrained devices. It provides a PQC integration to devices already in the field.
    Block Diagram -- Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
  • Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload
    • Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload, configurable as Subsystem or RoT, with SCA and FIA protection
    • Engineered for crypto and implementation agility, PQPlatform-TrustSys is optimized for PQ/T hybrid secure boot and features industry-leading protections against power, EM, and fault-injection attacks.
    Block Diagram -- Highly configurable HW PQC acceleration with RISC-V processor for full CPU offload
  • Agile PQC Public Key Accelerator
    • Agile IP comprised of HW/FW/SW, adaptable to future standards’ evolution
    • Highly configurable IP can be tuned for specific applications with most optimal PPA
    • Scalable PQC PKA IP complies with latest NIST PQC algorithms
  • xQlave® PQC ML-DSA (Dilithium)
    • Quantum-secure digital signatures for future-proof security
    • Compliant with ML-DSA standard by U.S. NIST
    • Pure RTL without hidden CPU or software components
    • Execution time is independent of any secret values
    Block Diagram -- xQlave® PQC ML-DSA (Dilithium)
  • Highly configurable HW Lattice PQC ultra acceleration in AXI4 & PCIe systems
    • PQPerform-Inferno is a powerful, scalable hardware solution engineered for unparalleled performance in the post-quantum era.
    • As a FIPS 140-3 CAVP-certified product, it provides a trusted foundation for next-generation security.
    Block Diagram -- Highly configurable HW Lattice PQC ultra acceleration in AXI4 & PCIe systems
  • Single instance HW Lattice PQC ultra accelerator
    • PQPerform-Flare is a powerful hardware-based FIPS 140-3 CAVP-certified product, designed for high throughput and low latency PQC.
    •  It adds PQC for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs.
    Block Diagram -- Single instance HW Lattice PQC ultra accelerator
  • Fully Digital Physically Unclonable Function (PUF) - PQC Ready
    • Secure storage without the use of any non volatile memory
    • No external key provisioning required
    • Does not require costly SRAM blocks
    • Proven reliability regarding voltage, temperature and aging with error probability much lower than 10-9
    Block Diagram -- Fully Digital Physically Unclonable Function (PUF) - PQC Ready
  • PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
    • eSi-Crystals is a hardware core for accelerating the high-level operations specified in the NIST FIPS 202, FIPS 203 and FIPS 204 standards.
    • It supports the Cryptographic Suite for Algebraic Lattices (CRYSTALS), it is lattice-based digital signature algorithm designed to withstand attacks from quantum computers, placing it in the category of post-quantum cryptography (PQC). 
    Block Diagram -- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
  • Agile Post Quantum Crypto (PQC) Public Key Accelerator - NIST algorithms
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • APB Post-Quantum Cryptography Accelerator IP Core
    • Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).
    • The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.
    Block Diagram -- APB Post-Quantum Cryptography Accelerator IP Core
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