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PCIe Gen6 IP

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Compare 19 IP from 8 vendors (1 - 10)
  • PCIe GEN6 PHY IP
    • The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer.
    • It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.
    Block Diagram -- PCIe GEN6 PHY IP
  • FPGA Proven PCIe Gen6 Controller IP
    • Supports up to x16 link width
    • Support for Tx/Rx cut-through
    • Supports 32 GT/s and 64 GT/s precoding
    • Supports 14-bit tags for TLPs (Transaction Layer Packets)
    • Supports buffering and credit management
    Block Diagram -- FPGA Proven PCIe Gen6 Controller IP
  • PCIe Gen6 Controller
    • NoC aware
    • Supporting speeds of up to 64 GT/s
    Block Diagram -- PCIe Gen6 Controller
  • PCIE Gen6 digital controller (Dual Mode)
    • Compliant wiPCIE Gen 6 Spec.
    • Compliant wiPipe 5.X Spec.
    • PrimeSOC’s PCIE Gen 6.O Core supports Flit and non – Flit Mode.
    • Supports X16, X8, X4, X2, X1 Lane Configuration.
  • PCIE Gen6 digital controller (Root Complex)
    • Compliant wiPCIE Gen 6 Spec.
    • Compliant wiPipe 5.X Spec.
    • PrimeSOC’s PCIE Gen 6.O Core supports Flit and non – Flit Mode.
    • Supports X16, X8, X4, X2, X1 Lane Configuration.
  • PCIE Gen6 digital controller (End Point)
    • Compliant wiPCIE Gen 6 Spec.
    • Compliant wiPipe 5.X Spec.
    • PrimeSOC’s PCIE Gen 6.O Core supports Flit and non – Flit Mode.
  • PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    • Based on silicon-proven PCIe 6.x controller design
    • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    Block Diagram -- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
  • PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    • Based on silicon-proven PCIe 6.x controller design
    • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    Block Diagram -- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
  • PCIe 6.0 (Gen6) Premium Controller
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    • Based on silicon-proven PCIe 6.x controller design
    • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    Block Diagram -- PCIe 6.0 (Gen6) Premium Controller
  • PCIe 6.0 (Gen6) Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    • Based on silicon-proven PCIe 6.x controller design
    • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    Block Diagram -- PCIe 6.0 (Gen6) Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
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