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PCIe Gen 3 IP

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Search (31)
Compare 31 IP from 14 vendors (1 - 10)
  • AXI PCI Express (PCIe) Gen 3
    • Maximum Payload Size (MPS) up to 256 Bytes
    • Messaged Signaled Interrupt (MSI)
    • Memory mapped AXI4 access to PCIe space
    • PCIe access to memory mapped AXI4 space
  • Low-jitter Ring PLL
    • 10MHz up to 640MHz input frequency range (65G)
    • 14MHz up to 2.8GHz output frequency range (65G)
    • Small footprint (0.02mm^2 in 65G
    • Integrated Long Term Jitter typically 1ps RMS -- meets requirements for PCIe gen 1, 2, 3 and SATA 1, 2, 3 reference clock
  • PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP
    • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
    • Supports 5.0Gbps and 10Gbps serial data transmission rate Supports 16-bit or 32-bit parallel interface Data and clock recovery from serial stream
    • Support 8b/10b encoder/decoder(5Gbps), 128/130 encoder/decoder(BGbps) and error indication
    • Tunable receiver detection to detect worse case cables
  • Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel
    • Single SERDES Design that meets wide range of Standards, Protocols and Speeds.
    • Any combination is possible, e.g. USB-3.0, PCIe Gen-3 and SATA Gen-3 in a single Combo SERDES.
    • Internal Low Jitter PLL support the various standards clocking requirements- no need for additional components.
    • Flexible Design- Tile Based Design that enable customer to select any number of Tx and Rx Lanes.
  • MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
    • Consumer Application SERDES
    • From 1.125Gb/s to 8Gb/s/ 10Gbs
    • Technology: 28FDSOI 8ML & 10ML
    • Support multi lane configuration
    Block Diagram -- MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
  • PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
    • Silicon Proven in GF 22GDX with 0.8V and 1.8V power supply.
    • Compatible with PCIe base Specification
    • Support 32-bit/16-bit parallel interface
    • Support for PCIe3(8.0Gbps)
    Block Diagram -- PCIe 3.0 Serdes PHY IP, Silicon Proven in GF 22FDX
  • ULL PCIe DMA Controller
    • PCIe Gen 3 (x16)
    • Ultra-fast transfer of data between FPGA logic and memory mapped user space
    • Multi-channel circular buffer architecture
    • Zero-copy circular buffers memory mapped to user space
  • AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
    • Maximum Payload Size (MPS) up to 256 Bytes
    • Messaged Signaled Interrupt (MSI)
    • Memory mapped AXI4 access to PCIe space
    • PCIe access to memory mapped AXI4 space
  • PCIe Gen1 PHY
    • ? 2.5-Gbps data transmission rate
    • ? Supports 16-bit interface at 250-MHz operation
    • ? Supports 32-bit interface at 125-MHz operation
    • ? Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
  • Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
    • - Quad PCIe 8/5/2.5 Gbps per lane
    • - Tight skew control of less than 1UI between lanes of the PMA
    • - Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
    • - Lowest latency
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