PCIe 5.0 Serdes PHY IP
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35
IP
from 6 vendors
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10)
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PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compliant with PCIe 5.0 Base Specification
- Compliant with PIPE 5.1
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s and 32GT/s
- Supported physical lane width: x4
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PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Compliant with PCIe 5.0 Base Specification
- Compliant with PIPE 5.1
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s and 32GT/s
- Supported physical lane width: x4
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PCIe 6.1 Controller
- Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
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PHY/PCS Logical Sub-Block IP Core for PCIe supporting PCIe 5.0, 4.0, 3.1 PHY/PMA and compliant to the PIPE 5.2 and 4.4.1 Specifications
- Compliant to the PIPE 5.2 Specification with Low Pin Count interface
- Compliant to the PIPE 4.4.1 Specification
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PCIe 5.0 PHY
- Advanced, built-in diagnostics including on-chip digital RX eye scope
- Internal/external loopback
- 8b/10b and 128b/130b encoding and decoding
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 40LP
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
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PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Compliant with PCIe 3.0 Base Specification
- Compliant with PIPE 4.3
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s and 8.0 GT/s
- Supported physical lane width: x4
