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PCI Express Switch IP

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Compare 110 IP from 9 vendors (1 - 10)
  • Multi-Port Switch IP for PCI Express
    • Designed according to the PCI Express 4.0, 3.1, 2.1, and 1.1 specifications, including the latest errata
    • Designed according to the PCI-SIG Single-Root I/O Virtualization specification
    • Supports PIPE PHY interface definition including variable clock and variable data
    • Supports 16.0, 8.0, 5.0 and 2.5 Gbps line rates
    Block Diagram -- Multi-Port Switch IP for PCI Express
  • PCI Express to AMBA 4 AXI/3 AXI Bridge
    • Complete IP solution consists of digital controllers, PHYs and verification IP
    • Fully supports the Synopsys Controller IP for PCI Express Endpoint, Root Port, Dual Mode (EP/RP), and Switch port types
    • Fully compliant with the AMBA 3 AXI and 4 AXI interconnects
    • Full protocol mapping from PCI Express to the AMBA 3 AXI or 4 AXI bus protocol
    Block Diagram -- PCI Express to AMBA 4 AXI/3 AXI Bridge
  • Controller IP for PCI Express 7.0
    • Supports all required features of the PCI Express 7.0 (128 GT/s) specification
    • Allows a full 128GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    • Advanced RAS-DES features for simplified bring-up and debug
    Block Diagram -- Controller IP for PCI Express 7.0
  • IP Compiler for PCI Express x8 (Soft IP)
    • Feature rich
    • Intellectual property (IP) compliant with PCI Express® (PCIe®) base specifications 1.0a and 1.1, with Gen1 x1, x4, and x8 lane support for endpoint applications
    • Optional end-to-end cyclic redundancy check (ECRC) and advanced error reporting (AER) for high-reliability applications
    • Ease of use
  • IP Compiler for PCI Express x4 (Soft IP)
    • Feature rich
    • Intellectual property (IP) compliant with PCI Express® (PCIe®) base specifications 1.0a and 1.1, with Gen1 x1, x4, and x8 lane support for endpoint applications
    • Optional end-to-end cyclic redundancy check (ECRC) and advanced error reporting (AER) for high-reliability applications
    • Ease of use
  • IP Compiler for PCI Express x1 (Soft IP)
    • Feature rich
    • Intellectual property (IP) compliant with PCI Express® (PCIe®) base specifications 1.0a and 1.1, with Gen1 x1, x4, and x8 lane support for endpoint applications
    • Optional end-to-end cyclic redundancy check (ECRC) and advanced error reporting (AER) for high-reliability applications
    • Ease of use
  • PCIe 6.2 Switch
    • 1 upstream port, up to 7 downstream ports
    • Up to 128 lanes
    • PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
    • L1 and wake-up events forwarding
    Block Diagram -- PCIe 6.2 Switch
  • Configurable CCIX controllers for CCIX 32G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
    • Supports all required features of the CCIX 1.1 specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s
    • Supports all required features of the PCI Express 5.0, 4.0, 3.1, 2.1 and 1.1 specifications
    • Supports up to sixteen 32.0 25.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
    • Available in 128-, 256- or 512-bit datapath widths for maximum flexibility
  • Automotive-grade controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
    • Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
    • Full Transaction Layer, Data Link Layer and Physical Layer
    • Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
    • Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
  • Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
    • Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
    • Full Transaction Layer, Data Link Layer and Physical Layer
    • Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
    • Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
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Semiconductor IP