PCI Express DMA IP
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26
IP
from 9 vendors
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DMA for PCI Express (PCIe) Subsystem
- DMA for PCI Express Subsystem connects to the PCI Express Integrated Block. Both IPs are required to build the PCI Express DMA solution
- Support for 64, 128, 256, 512-bit datapath for UltraScale+™, UltraScale™ devices. Support for 64 and 128-bit datapath for Virtex®-7 XT devices
- Up to 4 host-to-card (H2C/Read) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex-7 XT devices
- Up to 4 card-to-host (C2H/Write) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex-7 XT devices
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Lancero Scatter-Gather DMA Engine for PCI Express
- PCIe I/O performance: 200 MB/s x1 Gen 1 up to 3360 MB/s x8 Gen 2
- Easily connect logic and high-speed I/O peripherals to PCI Express
- Target Bridge supports Avalon Memory Mapped custom logic
- SGDMA Engine supports Avalon Streaming burst access devices
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Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- Comprehensive :
- Customizable :
- Supports :
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PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
- Designed to the USB4 Specification v1.0
- Follows PCIe 1.0 protocol, but can operate at any compatible speed
- Supports the PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
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PCI Express to VME64x Transparent Bridge
- Complete PCI Express to VME64x Master/Slave Bridge
- Improved performance compared to currently available ASIC solutions
- PCI Express x4 GEN1/2
- VME64x supported modes: SLT, BLT, MBLT, 2eVME and 2eSST
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High Channel Count DMA IP Core for PCI-Express
- Available for Xilinx or Intel (Altera) Devices
- User transmits / receives only user data without PCIe protocol
- AXI standard interfaces for easy integration
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Multi Channel DMA Flex IP Core for PCI-Express
- AXI standard interfaces for easy integration
- User transmits/receives only user data without PCIe protocol
- All AXI Interfaces have adjustable Datawidth and separate clocking
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PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe Interface
- Supported silicon:
- AMBA AXI Interface
- Data Engine and Address translation for PCIe-to-AXI and AXI-to-PCIe transfers
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PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe Interface
- Supported silicon:
- AMBA AXI Interface
- Data Engine and Address translation for PCIe-to-AXI and AXI-to-PCIe transfers
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Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
- Compliant with the PCI Express Base Specification 3.0
- Supported Lane width: x1, x2, x4 and x8
- Fully compliant with PCI Express transaction ordering rules
- Optimal buffering for high bandwidth Direct Memory Access (DMA) applications