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On-Chip Security IP

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Search (38)
Compare 38 IP from 14 vendors (1 - 10)
  • SoC Security Platform / Hardware Root of Trust
    • GEON-SoC is an area-efficient, processor-agnostic, hardware root of trust for SoC designs.
    • It implements secure boot and can optionally be enhanced to support firmware decryption and secure debug, or to act as a post-boot hardware security module (HSM).
    Block Diagram -- SoC Security Platform / Hardware Root of Trust
  • Hardware Security Module
    • Provides a hardware-based Root of Trust with a unique, immutable device ID
    • Supports cryptographic verification of device identity and integrity
    • Generate Public Key Infrastructure (PKI) keypairs that it can use to sign messages, including random number based challenges
    Block Diagram -- Hardware Security Module
  • GEON™ Secure Boot Hardware Engine
    • GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or otherwise insecure code.
    • The security platform employs public-key cryptography (which stores no secret on-chip) to ensure that only unmodified firmware from a trusted source is used by the system.
    Block Diagram -- GEON™ Secure Boot Hardware Engine
  • FlexNoC 5 Interconnect IP
    • Physical Awareness for faster timing closure
    • Higher margins
    • Fewer wires
    Block Diagram -- FlexNoC 5 Interconnect IP
  • High-speed Inline Cipher Engine
    • The ICE-IP-338 data path can be scaled to widths that are multiples of 128 bit to allow a tradeoff between area and performance that best fits the target application.
    • Configuration options include or exclude support for CipherText Stealing (CTS), the GCM mode, and the SM4 algorithm and/or Datapath Integrity logic.
    • The cryptographic AES and SM4 primitives can be provided with or without side channel attack DPA countermeasures.
    Block Diagram -- High-speed Inline Cipher Engine
  • Inline cipher engine with AXI, for memory encryption
    • Throughput: 128 bit (16 Byte) wide encryption/decryption per cycle
    • Throughput: 1 tweak computation per 4 clock cycles
    • Bidirectional design including arbitration between read and write requests
    • Zero clock overhead for switching between encryption (write) and decryption (read)
    • 30-40 cycle data channel latency
    Block Diagram -- Inline cipher engine with AXI, for memory encryption
  • Programmable Root of Trust With DPA and FIA for US Defense
    • Custom-designed 32-bit secure RISC-V processor
    • Multi-layered security model protects all core components against a wide range of attacks
    • Security model includes hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
    • State-of-the-art DPA resistance, FIA protection and anti-tamper techniques
    Block Diagram -- Programmable Root of Trust With DPA and FIA for US Defense
  • TLS 1.3 Compliant Crypto Coprocessor
    • NIST CAVP certified and OSCCA standard compliant crypto engine suite
    • Includes private/public key ciphers, message authentication code, hashes, and key derivation
    • Key wrapping function for the secure export of keys
    • Public-key coprocessor for digital signatures and key agreements over elliptic/Edward curves
    Block Diagram -- TLS 1.3 Compliant Crypto Coprocessor
  • HDMI 2.1 RX PHY 12Gbps in TSMC (16nm, 12nm)
    • Quad-pixel interface allows up to 48Gbps bandwidth data for uncompressed 8K resolution with 60Hz refresh rate
    • Fixed-rate stream with 16b18b decoding and de-scrambling
    • Supports latest object-based audio formats with 1536kHz sample rate and up to 32 channels
    • Dynamic metadata packets reception
  • HDMI 2.1 Rx PHY 12Gbps in Samsung (14nm)
    • Quad-pixel interface allows up to 48Gbps bandwidth data for uncompressed 8K resolution with 60Hz refresh rate
    • Fixed-rate stream with 16b18b decoding and de-scrambling
    • Supports latest object-based audio formats with 1536kHz sample rate and up to 32 channels
    • Dynamic metadata packets reception
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Semiconductor IP