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MPEG-H Audio IP

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Compare 12 IP from 10 vendors (1 - 10)
  • HDMI 2.0 Transmitter
    • Compliant with HDMI 2.0 specification and HDCP 1.4 Specification compliant
    • Supports high-definition video with up to 4K resolution
    • Support for up to 48-bit Deep Color
    • Supports industry-standard S/PDIF for digital audio using IEC 60958 2-channel PCM, and compressed (encoded) audio data (DTS, AC3, MPEG Audio) using IEC 61937 format
    Block Diagram -- HDMI 2.0 Transmitter
  • DAB modulator
    • Fully compliant with ETSI EN 300 401 V1.4.1 2006-06, for DAB
    • DAB-Modes: I, II, III, IV
    • All protection levels supported
    • Synchronous design
  • Multichannel Sound Controller
    • Multichannel sound controller for consumer electronics applications
    • Support S/PDIF and 4-channel I2S interfaces
    • Sound buffers of arbitrary size in external memory
    • Relaxed requirements for interrupt handling
  • Multi-rate Audio DAC/PLL Core
    • Operates from single 27/54MHz clock.
    • Ideal for MPEG, AC-3, DVD systems
    • Internally generates audio sample clocks
    • Multi-sample rates: 32, 44.1, 48 KHz
  • MPEG Transport Stream Multiplexing & Encapsulation Engine
    • MPEG Transport Stream Multiplexing & Encapsulation
    • RTP Encapsulation
    • Easy Integration
    Block Diagram -- MPEG Transport Stream Multiplexing & Encapsulation Engine
  • H.265/HEVC 422 10bit Decoder for 4K
    • Video stream
    • - Compliant with ITU-T H.265, ISO/IEC 23008-2
    • - Main / Main 12 Profile Level 1 to 6.1
    • - Input format: Annex. B
  • H.265/HEVC 422 10bit Encoder for 4K
    • Compliant with ITU-T H.265, ISO/IEC 23008-2
    • Main / Main 12 Profile Level 1 to 6.1
    • Input format: Annex. B
  • MPEG-1/2 + AAC Audio Decoder
    • MPEG-1/2 and AAC decoders are compliant with the ISO/IEC 11172-3, 13818-7, and 14496-3 audio standards, using Fraunhofer IIS high quality software
    Block Diagram -- MPEG-1/2 + AAC Audio Decoder
  • MPEG-2 Transport Stream Encapsulation for SMPTE2022
    • Brings full interoperability with VSF recommendations to carry SDI over SMPTE2022-1/2 using JPEG 2000 Broadcast profile in MPEG-2 TS over IP
  • 1394B I/O
    • Single-chip solution: The PHY IP can be combined with Link Layer IPs, creating smaller solutions. Additional components can be added to create a System On Chip (SOC) solution.
    • Flexible number of ports: Commercially available PHY chips have a fixed number of ports which for small peripherals is often overkill. On the other hand, host adapter would likely benefit from 3 or more ports and a hub could even have more than that. For a PHY based on FPGA technology, the user can customize the number of ports as required.
    • Optional debug and test features: Optionally the user can include debug and test features like BERT (Bit Error Rate Test) Low level data monitoring and recording
    • Field-upgradable: The used FPGAs are field upgradable thus allowing the addition new features or bug fixes, even if the device is already in the field.
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