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Search (18)
Compare 18 IP from 7 vendors (1 - 10)
  • Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
    • The only Multi-Threaded Out-of-Order RISC-V Core with ASIL-B Certification
    • Highly scalable multi-core, multi-cluster, coherent computing solution
    • MIPS extensions for improved performance and functionality
    • Use in Automotive, Datacenter, and Embedded applications
    Block Diagram -- Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
  • I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU

    • The DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.

      The DB-I2C-S-SCL-CLK-APB, in the I2C Slave Controller Core managing the I2C protocol & physical layer, contains no free running clock, while interfacing through dual clock FIFOs to the AMBA APB Bus, for a low power, low noise Microprocessor interface to the I2C Bus. The I2C Slave Controller Core runs off the external SCL clock while the APB side off the APB Clock.

    Block Diagram -- I2C Controller IP – Slave, SCL Clock, Parameterized FIFO, APB Bus. For low power requirements in I2C Slave Controller interface to CPU
  • Bluetooth Connectivity Platform
    • The Ceva-Waves Bluetooth platform comprises a comprehensive set of hardware IP, software modules, and radios from Ceva and third-party partners addressing a broad choice of processes and nodes, to implement highly efficient Bluetooth connectivity in SoCs.
    • The latest Bluetooth standards, both Bluetooth LE and dual-mode versions are supported, and an available add-in extends support to IEEE 802.15.4.
    Block Diagram -- Bluetooth Connectivity Platform
  • Image Signal Processor IP enabling high performance real-time image processing
    • Support DVP Input Interface
    • Support 8-16 Bit Bayer RAW and ITU-R BT.601 & 656 Video Interface
    • Test Pattern Generator (TPG)
    • Black Level Measurement and Compensation (BLS)
    • Sensor Linear Correction
  • USB 2.0 Digital Controller IP
    • Fully supports Hi-Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) (USB 2.0 Speeds) specifications
    • Configurable root hub supports 1 to 15 downstream ports
    • 60MHz or 30MHz input clock, and 48MHz and 12MHz input clocks
    • ULPI and UTMI+ interfaces for rapid PHY integration
  • USB 1.1 Digital Controller IP
    • Fully supports USB Full Speed and Low Speed (USB 1.1 Speeds)
    • Configurable root hub supports 1 to 15 downstream ports
    • Integrated DPLL simplifies transceiver integration
    • Low gate counts, starting at 30k gates
  • SD/SDIO 2.0 MMC Host Controller
    • Host controller for SDIO, SD memory card, and MMC interface.
    • Allows host CPU to access SD and MMC devices.
    • Simple user interface optimized for on-chip bus connection.
    • User interface supports 32-bit and 64-bit data.
    Block Diagram -- SD/SDIO 2.0 MMC Host Controller
  • CompactFlash/PCMCIA Host Controller with EXCA Registers
    • Compliant with PC Card Standard 8.0, PCMCIA 2.1/JIEDA 4.2 and CompactFlash 1.4.
    • Allows host CPU to access CompactFlash, PC Card/PCMCIA devices.
    • 82365SL-compatible register set, EXCA compatible.
    Block Diagram -- CompactFlash/PCMCIA Host Controller with EXCA Registers
  • I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
    • The DB-I2C-S-AHB Controller IP Core interfaces a NIOS II, ARM, MIPS, PowerPC, ARC or other high-performance microprocessor via the Avalon System Interconnect Fabric to an I2C Bus.
    • The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices.

    The DB-I2C-S-AVLN is a Slave I2C Controller that controls the Transmit or Receive of data to or from external Master I2C devices. Figure 1 depicts the system view of the DB I2C-S-AVLN Controller IP Core embedded within an integrated circuit device.

    Block Diagram -- I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
  • I3C Controller IP – Master, Parameterized FIFO, APB Bus
    • The DB-I3C-M-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improved Inter Integrated Circuit specification.
    • The I3C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I3C devices as well as legacy I2C Slave devices.
    • The DB-I3C-M-APB is an I3C Master Controller supporting I3C SDR / Broadcast / Direct Messages, Legacy I2C Message, and I3C HDR Mode (optionally).
    Block Diagram -- I3C Controller IP – Master, Parameterized FIFO, APB Bus
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