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MIPI C/D-PHY Combo IP

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Compare 27 IP from 7 vendors (1 - 10)
  • MIPI C/D-PHY Combo IP
    • Compliant to MIPI D-PHY v3.0, C-PHY v2.1 specification
    • Area efficient macro optimized for placement for dense SoC designs
    • Support Uni-(TX or RX) and Bi-directional(TX and RX) mode
    • Support emphasis architecture over lossy channel for TX
    • Support equalize architecture over lossy channel for RX
    Block Diagram -- MIPI C/D-PHY Combo IP
  • MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 40 LP
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 40 LP
  • MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 40 LP
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 40 LP
  • MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 28 HPC+
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 28 HPC+
  • MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 28 HPC+
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 28 HPC+
  • MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 22 ULP
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 22 ULP
  • MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 22 ULP
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 22 ULP
  • MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 16 FFC
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 16 FFC
  • MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 16 FFC
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 16 FFC
  • MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 12 FFC
    • Compliant with MIPI D-PHY spec up to v2.5 and C-PHY spec up to v2.0
    • Support both MIPI DSI and CSI-2 protocols
    • Support HS data rate up to 6Gbps ( 6Gsps ) per lane (per trio)
    • Support LS data rate of 10Mbps and Ultra-low power mode
    Block Diagram -- MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 12 FFC
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