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MACsec IP

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Compare 54 IP from 10 vendors (1 - 10)
  • MACsec - Extreme-Speed Variant
    • Moderate resource requirements
    • Performance
    • Standard Compliance
    Block Diagram -- MACsec - Extreme-Speed Variant
  • Media Access Control Security (MACSec)
    • Up to four ports of concurrent traffic with an aggregate bandwidth of 100G are supported by one core (1x100G, 2x50G, 2x40G, 4x25G, 4x10G, 4x1G, 1x50G+2x25G)
    • Line rate operation
    • Flexible control/non-control port filtering
    • Configurable number of Secure Channels (SCs) and Security Associations (SAs) per physical port
    Block Diagram -- Media Access Control Security (MACSec)
  • Secure-IC's Securyzr™ 1.5Tbps MACsec Engine
    • Throughput up to 1.5Tb
    • ASIC and FPGA
    • Multi-channel support for link aggregation or FlexE
    Block Diagram -- Secure-IC's Securyzr™ 1.5Tbps MACsec Engine
  • MACsec Protocol Engine for 10/100/1000 Ethernet
    • Compliant to IEEE 802.1AE-2018 and IEEE 802.1AEbw.
    • Implements both GCM-AES and GCM-AES-XPN modes with 128- and 256-bit keys.
    Block Diagram -- MACsec Protocol Engine for 10/100/1000 Ethernet
  • MACsec 10G/25G
    • Compliance with IEEE Std 802.1AE-2018
    • Line-rate traffic encryption and decryption
    Block Diagram -- MACsec 10G/25G
  • IEEE 802.1ae (MACsec) Security Processor
    • Small size combined with high performance:
    • Self-contained, uses two external memories for key storage and statistic counters
    • Very low latency
    • Back-to-back packet processing
    Block Diagram -- IEEE 802.1ae (MACsec) Security Processor
  • P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core
    • Small size: From 60K ASIC gates (at throughput of 18.2 bits per clock)
    • 487 MHz frequency in 90 nm process
    • Easily parallelizable to achieve higher throughputs
    • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
    Block Diagram -- P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core
  • MACsec - High-Speed Variant
    • Moderate resource requirements
    • Performance
    • Standard Compliance
    Block Diagram -- MACsec - High-Speed Variant
  • MACsec - Balanced Variant
    • Optimised resource requirements
    • Compliant with IEEE 802.1AE-2018
    • Powered by AES256-GCM
    • Pure RTL without hidden CPU or software components
    Block Diagram -- MACsec - Balanced Variant
  • Combo P1619 / 802.1ae (MACSec) GCM-AES/LRW-AES Cores
    • Small size: from 31,000 ASIC gates for GLM1 from 58,000 ASIC gates for GLM2
    • 400 MHz frequency in 130 nm process GLM1 throughput is 12.8 bits per clock GLM2 throughput is 25.6 bits per clock
    • Easily parallelizable to achieve higher throughputs
    • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
    Block Diagram -- Combo P1619 / 802.1ae (MACSec) GCM-AES/LRW-AES Cores
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