Low Voltage SRAM IP
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Single Port Low Voltage SRAM Memory Compiler on N22ULL - Low Power Retention and Column Repair
- Ultra-Low Leakage: High VT (HVT) are used to minimize leakage performance
- Bit Cell: Utilizes Low Leakage 6T bit cells to ensure high manufacturing yields
- Ultra Low Power Standby: Internally generated bias voltage for low leakage data retention
- Isolated Array and Periphery supplies: Periphery voltage can be shut off to further reduce standby power
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Single Port Low Voltage SRAM Memory Compiler on N22ULL
- Ultra-Low Leakage: High VT (HVT) are used to minimize leakage performance
- Bit Cell: Utilizes Low Leakage 6T bit cells to ensure high manufacturing yields
- Ultra Low Power Standby: Internally generated bias voltage for low leakage data retention
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 72 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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Dual Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- 1.Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- 2.Extend the battery life
- Leakage reduction thanks to careful design structures, optional retention mode and choice of SVT/HVT periphery
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UMC 40nm embedded high voltage (eHV) low power Process standard synchronous high density single port register file SRAM memory compiler.
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Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- REACH THE HIGHEST DENSITY
- Thanks to smart periphery design
- Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
- Using Pushed Rules Foundry bitcell
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Foundry sponsored - Single Port SRAM compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 320 k
- FOUNDRY SPONSORED
- HIGHEST DENSITY
- -Smart periphery design
- -Typically up to 20% gain in density versus alternative HD-LP RAM depending on instance configuration
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Single Port SRAM compiler - Memory optimized for high density and low power - Dual voltage - compiler range up to 640 k
- Migration on an existing architecture already available for other processes (90, 85, 55 nm)
- Configuration
- SVT transistors for memory periphery
- uHD HVT Pushed rule bit cell from foundry