LPDDR4 memory IP
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117
IP
from 11 vendors
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DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+)
- Supported DRAM type: DDR3L/DDR4/LPDDR4
- Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
- Interface: SSTL135/POD12/LVSTL
- Data path width scales in 32-bit increment
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LPDDR 4/4X PHY, TSMC 12E, N/S orientation
- Multi-interface support: LPDDR4 up to 4267Mbps, LPDDR4X up to 4267Mpbs
- Supports LPDDR4X 0.6V VDDQ
- Optimized for high performance and integration flexibility. The harden IP included 8-bit data blocks, 6-bit C/A blocks, clock blocks, PLL and DLL. IP pin-out can be configured to optimize for LPDDR4/4X.
- High resolution read/write timing control
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DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
- Support DDR3 / DDR3L / DDR4/ 3DS DDR4/ LPDDR4 / MRAM
- Support x8/x16/x32 DRAM data bus configuration (programmable)
- Support Multi-Ranks DRAM configuration
- DDR base on DFI spec 4.0 compliant.
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Performance Enhanced version of DDR Enhanced Memory Ctl (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
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Performance Enhanced version of uMCTL2 supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3 and LPDDR2 for Automotive
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
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DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
- Select a complete multi-ported Enhanced Universal DDR Memory Controller offering 1 to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Protocol Controller
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs
- Compatible with all Synopsys DDR PHYs (excluding DDR2/DDR PHYs) using DFI-compliant interfaces
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LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X
- Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
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LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
- Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
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LPDDR Controller ASIL B Compliant supporting LPDDR5, LPDDR4 and LPDDR4X for Automotive Applications
- Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
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LPDDR Secure Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
- Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
- Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
