Interface IP

The MACsec-IP-364 is a MACsec/IPsec engine developed specifically for high-speed, multi-rate and multi-port Ethernet devices.
Its architecture provides an optimal multi-protocol solution for aggregate throughput for 1.6T and 3.2T.
The MACsec-IP-364 is ideal for deployment in data center, enterprise and carrier network applications, as well as network-attached high-performance computing.

The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DDR3/DDR4 SDRAM memories.
The synthesizable RTL (ddr_phy_top) provides control functions such as initialization, SDRAM interface training, impedance calibration and programmable configuration controls.

The USB PHY IP is UTMI interface compatible and a dedicated circuit for full-function USB 2.0 transceivers.
It is a mixed-signal circuit, with the analog part including the transmitting and receiving circuits, level conversion circuits, bus driver circuits, etc., and the digital part including the transmitting and receiving and speed switching control circuits, encoding and decoding circuits, serial-to-parallel and parallel-to-serial conversion circuits, as well as digital CDR circuits, etc.

Supports image and video capturing of DVP interface camera (GC0308/OV5640)
Supports image and video capturing of parallel digital video decode chip (TVP5150)
Supports 8-, 10-, 12-, 14-, 16-bit parallel input data

The IP block provides the physical layer implementation of ISO 14443 interface. In particular, it includes the necessary functional devices for receiving data on the connected antenna, for the response load modulation, received and transmitted data (de)framing and parallel interface to external CPU.
This IP also can be used for adding NFC functionality to mobile devices and other applications to perform high-level RFID protocol tasks.

The IP block provides the physical layer implementation of ISO 14443 interface. In particular, it includes the necessary functional devices for receiving data on the connected antenna, for the response load modulation, received and transmitted data (de)framing and parallel interface to external CPU.
This IP also can be used for adding NFC functionality to mobile devices and other applications to perform high-level RFID protocol tasks.

ION 64b66b is an IP for high-speed serial interface targeting applications with inter-chip and inter-board connections.
Lightweight link layer protocol provides one-to-one data movement via one or more high-speed serial lanes.

ION 8b10b is a high-speed serial interface targeting applications with inter-chip and inter-board connections.
Lightweight link layer protocol provides one-to-one data movement via one or more high-speed serial lanes.

QSGMII (Quad Serial Gigabit Media Independent Interface) IP from Comcores is a high-speed serial interface developed to aggregate four Gigabit Ethernet (SGMII) ports into a single high-speed serial link using 8b/10b encoding at 5 Gbps.
It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.

The USXGMII PCS IP provides the logic required to integrate a USXGMII-M IP into any system on chip (SoC).
Link speeds of 5G, 10G, or 20G are supported. Compliant with the Cisco Universal SXGMII Interface for multiple Multi-Gigabit Copper Network Ports and IEEE 802.3 Clause 49 standards, the PCS IP has several optional features to customize the physical coding sublayer (PCS) for the specific needs of any application.