Interface IP

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Compare 6,740 IP from 348 vendors (1 - 10)
  • USB 2.0 Human Interface Devices Design Platform
    • The USB 2.0 HID Design Platform is a complete, integrated solution, dedicated to a wide range of USB-based Human Interface Devices, like mouse, keyboard, and tablet.
  • MIPI CPHY v1.1 Analog Interface
    • The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
    • It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0).
    • The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY.
    Block Diagram -- MIPI CPHY v1.1 Analog Interface
  • Combination MIPI CPHY-DPHY Analog Interface
    • The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
    • It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0).
    • The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires
    Block Diagram -- Combination MIPI CPHY-DPHY Analog Interface
  • LVDS Tunneling Protocol and Interface (LTPI) IP
    • LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 Specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.
    Block Diagram -- LVDS Tunneling Protocol and Interface (LTPI) IP
  • Expanded Serial Peripheral Interface (xSPI) Slave Controller
    • The JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface(SPI) devices
    • It is used to connect xSPI Master devices in computing, automotive, Internet of Things, Embedded system and mobile system processor to non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
    Block Diagram -- Expanded Serial Peripheral Interface (xSPI) Slave Controller
  • Expanded Serial Peripheral Interface (xSPI)Master Controller
    • The Expanded Serial Peripheral Interface (JESD251) Master controller is low signal count, high data bandwidth, primarily for use in computing, automotive, Internet of Things, Embedded system and mobile system processor to connect multiple source of Serial Peripheral Interface (xSPI) slave devices like non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
    Block Diagram -- Expanded Serial Peripheral Interface (xSPI)Master Controller
  • DDR5 Serial Presence Detect (SPD) Hub Interface
    • The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), from master host bus
    • This SPD5 has Two wire serial interface like SCL, SDA
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    Block Diagram -- DDR5 Serial Presence Detect (SPD) Hub Interface
  • MIPI CSI -2 TRANSMITTER IP -V3
    • MIPI CSI-2 (Camera Serial Interface) Transmitter IP defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications
    • The MIPI CSI-2 Transmitter IP provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
    Block Diagram -- MIPI CSI -2  TRANSMITTER IP -V3
  • MIPI CSI-2 V3 RECEIVER INTERFACE IP
    • The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications
    • The MIPI CSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
    Block Diagram -- MIPI CSI-2 V3 RECEIVER INTERFACE IP
  • ETSI SSP I3C Interface
    • The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Common Layer (SCL) protocol
    • The use of the MIPI I3C Basic bus specification provides the ETSI SSP with a multitude of benefits, such as higher data rate, flexible and efficient information exchange, and strong integration of SSP in connected devices
    Block Diagram -- ETSI SSP I3C Interface
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Semiconductor IP