IEEE 1588 IP
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88
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IEEE 1588 Boundary, Slave And Master Clock
- IEEE 1588 v2 compliant Boundary Clock and Master/Slave Ordinary Clock IP core
- ToD error is better than ±1µsec on a managed 10-switch GbE network under ITU-T G.8261 conditions
- Frequency accuracy performance is better than 16ppb on a managed 10-switch GbE network under ITU-T G.8261 conditions
- Standard compliant Best Master Clock (BMC) algorithm
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10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
- Fully compliant core with proven silicon
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
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Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
- General Functions:
- Hardware support for IEEE 1588 V1 and V2
- Transmit Functions:
- Receive Functions:
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Fast Ethernet 10/100 802.3 MAC with IEEE 1588 PTP Support
- General Functions:
- Transmit Functions:
- Receive Functions:
- Flow Control Functions:
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IEEE 1588 IP
- Compliant with IEEE Standard 1588-2019 specification
- Configurable as PTP Master or PTP Slave
- Supports both end to end and peer to peer delay mechanism
- Generates timestamp based on Real time clock (high precision clock)
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IEEE 1588 V2 Ordinary and Boundary Clock
- Hardware features:
- Software features:
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IEEE 1588 V2 CPU-less Slave Clock
- IP core netlist ready for seamless integration in ISE design flow
- Reference design for AVNET Spartan-6 FPGA LX9 Microboard
- Available profiles: Power, IEC 61850 and Telecom
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IEEE 1588 Boundary, Slave And Master Clock
- Standalone IEEE1588v2 standard compliant BC and Master/Slave OC chip on FPGA
- Hybrid 1588/SyncE mode support
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IEEE 1588 Boundary, Slave And Master Clock
- Standalone IEEE 1588 v2 standard compliant Boundary Clock (BC) and Ordinary Clock (OC) Master/Slave IP core for Xilinx Spartan-6
- Excellent synchronization performance over most extreme packet transport network conditions
- Slave meets 3G, 4G-LTE and 5G synchronization requirements
- Adaptive to network impairments
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syn1588® enabled IEEE 1588 compliant clock synchronisation
- fully synchronous to the system clock
- all registers of the core operate with the rising clock edge
- well commented, structured VHDL source code
- medium footprint and medium I/O count
