I2S IP
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I2S - Ensures proper audio data transmission, synchronization, and integrity
- I2S (Inter-IC Sound) is a serial bus interface used for connecting digital audio devices. As a Verification IP (VIP), it ensures proper data transmission, signal integrity, timing, and protocol compliance in audio communication systems.
- This VIP verifies key elements such as word length, frame synchronization, clock behavior, and error handling, making it essential for testing I2S communication in a range of applications, including consumer electronics, automotive, and medical devices
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Simulation VIP for I2S
- Configurability
- Fully configurable VIP configuration: Manager/Subordinate, Transmitter/Receiver, Active/Passive
- Word Length Programmability
- Supports 8, 12, 16, 20, 24, 32, and user-defined
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I2S Verification IP
- Complies with Philips I2S Specification June 5, 1996
- Full I2S Transmitter, Receiver and Controller functionality
- Supports up to 32 channels in transmit path
- Supports up to 32 channels in receive path
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I2S Synthesizable Transactor
- Supports Philips I2S Bus Specification June 5, 1996
- Full I2S Transmitter, Receiver and Controller functionality
- Supports up to 32 channels in transmit path
- Supports up to 32 channels in receive path
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I2S Controller IIP
- Compliant with the Philips I2S Bus Specification
- Master mode as Controller
- Slave mode as transmitter and receiver
- Bidirectional operation through two unidirectional serial data lines
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Dolphin I2S Controller & PHY
- Support Master only and Slave only and Master & Slave operation
- I2S, left-justified, right-justified mode
- Audio bit-depth 8/12/16/24/32
- Stereo audio
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Audio I2S
- AXI4S Compliant
- Can be configured up to 4 I2S interfaces, each channel supporting 2 audio channels
- Can be configured up to 4 stereo or 8 independent channels
- 16/24 bit data support
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I2S Controller IP Core- Two Channel
- Complies with Philips* I2S Specification
- Supports two I2S channels
- Simultaneous audio playback and recording
- Supports configurable 8/16/24/32 bit DAC/ADC resolution
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I2S Receiver/Transmitter
- Configurable structure
- OPB V2.0 bus interface for access into internal registers
- PLB V3.4 bus interface for off-chip memory access
- Adjustable memory interface width 16, 32, or 64 bits