I2S IP
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121
IP
from 24 vendors
(1
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10)
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I2S Controller IP
- Compliant with the Philips I2S Bus Specification
- Master mode as Controller
- Slave mode as transmitter and receiver
- Bidirectional operation through two unidirectional serial data lines
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Dolphin I2S Controller & PHY
- Support Master only and Slave only and Master & Slave operation
- I2S, left-justified, right-justified mode
- Audio bit-depth 8/12/16/24/32
- Stereo audio
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Audio I2S
- AXI4S Compliant
- Can be configured up to 4 I2S interfaces, each channel supporting 2 audio channels
- Can be configured up to 4 stereo or 8 independent channels
- 16/24 bit data support
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I2S Controller IP Core- Two Channel
- Complies with Philips* I2S Specification
- Supports two I2S channels
- Simultaneous audio playback and recording
- Supports configurable 8/16/24/32 bit DAC/ADC resolution
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I2S Receiver/Transmitter
- Configurable structure
- OPB V2.0 bus interface for access into internal registers
- PLB V3.4 bus interface for off-chip memory access
- Adjustable memory interface width 16, 32, or 64 bits
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I2S/TDM Multichannel Audio Transceiver
- Supports left-justified and right-justified I2S and TDM audio data formats
- Full-duplex operation
- Configurable number of receive and transmit data lines (pins), and number of audio channels
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I2S/TDM Serial Audio Interface with Asynchronous Sample Rate Conversion
- Integrating this unique component will eliminate a discrete component in the bill of materials
- Support for both FPGA and ASIC with seamless transition
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Audio I2S-TDM Transceiver
- Full duplex operation for maximum 10 receive pins and 10 transmit pin
- High-channel count, for example, 86 48KHz/24-bit channels for a 100MHz bit clock frequency
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I2S/Left-Justified/TDM Digital Audio Interface
- I2S/Left-Justified/TDM-A/TDM-B Formats
- Master/Slave Dual Operation