I2C/SPI Controller IP

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Compare 35 IP from 14 vendors (1 - 10)
  • I2C and SPI Master/Slave Controller
    • The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit) protocols.
    • Its low silicon resource requirement makes it suitable for area-constrained and low-power applications, while its software compatibility with Microchip’s MSSP peripheral eases use and software integration.
    Block Diagram -- I2C and SPI Master/Slave Controller
  • MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
    • Conforms to MIPI I3C v1.1 specifications
    • MIPI Manufacturer ID: 0x03B3
    • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
    • Legacy I2C messaging
  • Analog Data Acquisition Controller IP
    • AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
    • User configurable acquisition parameters: Sampling frequency, number of samples in bursts.
    • Programmable ADC interface to connect different types of ADCs in addition to analog multiplexers to connect multiple analog channels
    • Optimized power consumption
    Block Diagram -- Analog Data Acquisition Controller IP
  • MIPI I3C Master Controller
    • Compliant with the latest MIPI I3C specification
    • Backward compatible with the I2C slave devices
    Block Diagram -- MIPI I3C Master Controller
  • MIPI I3C Slave Controller
    • Compliant with the latest MIPI I3C specification
    • Backward compatible with the I2C slave devices
    • Supports all data rates up to 26.7 Mbps
    • Optional High Data Rate messaging Modes (HDR)
    Block Diagram -- MIPI I3C Slave Controller
  • 16Bit 91dB Audio CODEC with headphone drivers and PWM Controller, SMIC0.18um
    • DAC 91dB SNR, ADC 85dB SNR Audio Mono CODEC
    • PWM Controller for Class-D Amplifier Configuration
    • Capacitor-less dual channel headphone Output
    • 8KHz to 48KHz Sampling Frequency
  • Generic Platform IP for Micro-Controllers
    • Supports AndesCore™ N7/N8/N9/N10
    • Provides two bus structures
    • Provides interfaces for design extension/integration
    Block Diagram -- Generic Platform IP for Micro-Controllers
  • Block Diagram -- LatticeMico32 Open, Free 32-Bit Soft Processor
  • Lattice Mico8 Open, Free Soft Microcontroller
    • Innovative Open IP Core License
    • Efficient Architecture and Broad Feature Set
    • Wishbone Peripheral Components:
    Block Diagram -- Lattice Mico8 Open, Free Soft Microcontroller
  • AXI Subsystem
    • The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces such as the BA20, BA21, and several RISC-V Implementations.
    • The AXI Subsystem combines peripheral and interface IP cores with drivers and other essential software and an AXI/APB bus infra- structure.
    Block Diagram -- AXI Subsystem
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Semiconductor IP