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Hashing engine IP

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Compare 12 IP from 5 vendors (1 - 10)
  • ASCON Authenticated Encryption & Hashing Engine
    • The ASCON-F IP core is a compact, high-throughput hardware engine implementing the lightweight authenticated encryption with associated data (AEAD) and hashing algorithms described in the Ascon v1.2 specification. 
    • A single instance of the ASCON-F IP core can encrypt or decrypt data using the Ascon-128 and Ascon-128a functions or perform Cryptographic hashing Hash per the Ascon-Hash and Ascon-Hasha functions.
    Block Diagram -- ASCON Authenticated Encryption & Hashing Engine
  • GEON™ Secure Boot Hardware Engine
    • GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or otherwise insecure code.
    • The security platform employs public-key cryptography (which stores no secret on-chip) to ensure that only unmodified firmware from a trusted source is used by the system.
    Block Diagram -- GEON™ Secure Boot Hardware Engine
  • Keccak Hash Engine
    • The Keccak Hash crypto engine is an IP core and built with a focus on simplicity and seamless integration, while also following coding and verification practices in the industry.
    • It operates in a single clock domain and has been extensively verified.
    • It can be flexibly configured and customized to support different output lengths and security levels.
  • SHA-3 Crypto Engine
    • FIPS 202 and FOS 180-4 compliant
    • SHA3-224, SHA3-256, SHA3-384, SHA3-512
    • SHAKE-128, SHAKE-256
    Block Diagram -- SHA-3 Crypto Engine
  • SHA-3 Secure Hash Crypto Engine
    • The SHA-3 is a high-throughput, area-efficient hardware accelerator for the SHA-3 cryptographic hashing functions, compliant to NIST’s FIPS 180-4 and FIPS 202 standards. 
    • The accelerator core requires no assistance from a host processor and uses standard AMBA® AXI4-Stream interfaces for input and output data.
    Block Diagram -- SHA-3 Secure Hash Crypto Engine
  • Hash Crypto Engine
    • ASIC and FPGA
    • Supports:
    • Supports HMAC
    • Message padding in software or hardware
    Block Diagram -- Hash Crypto Engine
  • SHA-3 Crypto IP Core
    • FIPS 202 compliant
    • Supports cryptographic hashing for SHA-3 in 224/256/384/512 mode
    • Extendable-Output Functions for SHAKE 128/256
    • AMBA® AXI4-Stream 
    Block Diagram -- SHA-3 Crypto IP Core
  • Multipurpose Security Protocol Accelerator
    • Highly configurable security accelerator
    • Support for all ciphers, hashes and MAC algorithms used in major protocols such as IPsec, SSL/TLS/DTLS, Wi-Fi, 3GPP LTE/LTE-A, SRTP, MACsec
    • Cipher algorithms: AES, DES/3DES, ChaCha20, MULTI2, KASUMI, SNOW 3G, ZUC
    • Cipher modes: ECB, CBC, CTR, OFB, CFB, f8, XTS, UEA1, UEA2, 128-EEA1, 128-EEA2, 128-EEA3
  • Multipurpose Security Protocol Accelerator - Functional Safety ASIL B support
    • Highly configurable security accelerator
    • Support for all ciphers, hashes and MAC algorithms used in major protocols such as IPsec, SSL/TLS/DTLS, Wi-Fi, 3GPP LTE/LTE-A, SRTP, MACsec
    • Cipher algorithms: AES, DES/3DES, ChaCha20, MULTI2, KASUMI, SNOW 3G, ZUC
    • Cipher modes: ECB, CBC, CTR, OFB, CFB, f8, XTS, UEA1, UEA2, 128-EEA1, 128-EEA2, 128-EEA3
  • Security Enclave IP based on RISC-V
    • Secure Boot
    • Firmware update in the field
    • Secure key storage
    Block Diagram -- Security Enclave IP based on RISC-V
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