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Encryption IP

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Compare 483 IP from 74 vendors (1 - 10)
  • AXI2AXI encryption bridge
    • The PLUG module is a silicon-proven AXI-to-AXI bridge designed to provide data encryption and inline ECC for reliable and secure communication.
    • It supports AXI4 protocol with bursts and integrates seamlessly into systems handling DMA, CPU, or cache streams.
    • For write transactions, it encrypts data and appends ECC, while for reads, it decrypts and validates/corrects ECC.
    Block Diagram -- AXI2AXI encryption bridge
  • Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode
    • The ICE-IP-63 (EIP-63) is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES-CTR and GMAC on bulk data.
    • Its flexible data path is suitable to scale from 100 Gbps to 2.4 Tbps to provide a tailored engine with minimal area for your application.
    • The FIFO-like data interface makes it possible to perform frame processing for many different protocols, including MACsec, IPsec, and OTN security. 
    Block Diagram -- Inline cipher engine for PCIe, CXL, NVMe, 5G FlexE link integrity and data encryption (IDE) using AES GCM mode
  • Inline cipher engine with AXI, for memory encryption
    • Throughput: 128 bit (16 Byte) wide encryption/decryption per cycle
    • Throughput: 1 tweak computation per 4 clock cycles
    • Bidirectional design including arbitration between read and write requests
    • Zero clock overhead for switching between encryption (write) and decryption (read)
    • 30-40 cycle data channel latency
    Block Diagram -- Inline cipher engine with AXI, for memory encryption
  • Inline memory encryption engine, for FPGA
    • Performs encryption, decryption and/or authentication using AES Counter Mode (CTR) or Galois Counter Mode (GCM)
    • Supports AES key sizes 128 or 256
    • Internal key management with NIST-compliant key generation
    • Encrypt memory space into user-defined vaults, each with a unique key
    • Compatible with AMBA AXI4 interface
    • Supports hard or soft memory controllers in Xilinx FPGA and SoC devices
    • Supports multiprocessor systems
    Block Diagram -- Inline memory encryption engine, for FPGA
  • Inline memory encryption engine for ASIC SoCs
    • 128/512-bit (16-byte) encryption and decryption per clock cycle throughput
    • Bidirectional design including separate crypto channels for read and write requests, ensuring non-blocking Read
    • Read-modify-write supporting narrow burst access.
    • Zeroization and support for memory initialization
    • Latency: <28 clock cycles for unloaded READ
    Block Diagram -- Inline memory encryption engine for ASIC SoCs
  • ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
    • Compliant with PCI Express IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • Automotive compliant (ASIL B) aligning with ISO 26262 and ISO/SAE 21434
    Block Diagram -- ASIL B Compliant PCIe 5.0 Integrity and Data Encryption Security Module (select configurations)
  • PCIe 6.0 Integrity and Data Encryption Security Module
    • Compliant with PCI Express IDE specification
    • Support for TDISP
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • FLIT mode support
    Block Diagram -- PCIe 6.0 Integrity and Data Encryption Security Module
  • AES 256 encryption IP core
    • Data Path runs at 256-bit width.
    • Programming of Key and Initialization Vector Supported.
    • Buffer-free implementation of RTL code is fast and easy to integrate into SoCs.
    • Pipelined instances architecture with Vendor-independent code.
  • PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
    • Full support of PCI Express 7.0 (64GT/s) IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
  • Advanced Encryption Standard compliant with FIPS 197
    • Support for 128 and 256 key bit length
    • Support for ECB, CBC, CFB, OFB, CTR block cipher modes
    • Internal key expansion module
    • Flexible data read/write modes
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