Encryption IP

The Helion G.9961 AES-CCM (“AES-G.hn”) core is designed to sit near the top of the LLC sublayer and provide the security functionality described in Section 9.1 of ITU-T G.9961.
The core integrates all of the underlying functions required to implement AES in CCM mode for G.9961 including nonce and header formation, round-key expansion, counter management, block chaining, final block masking, and tag appending and checking features.
The only external logic required is to insert the CCMP header field for frames that are to be encrypted.

The Stealth AES Encryption IP provides advanced encryption capabilities to secure data transmission and storage in various applications, including IoT devices, edge computing systems, cloud platforms, and communication networks.
Built on the Advanced Encryption Standard (AES), our IP offers robust encryption algorithms to safeguard sensitive information against unauthorized access and data breaches.

AES core implements the Rijndael algorithm for encryption and decryption of plain text using cipher keys.
It is compliant with FIPS 197 standards. The core works with a pre-expanded key, or with optional key expansion logic.
The encryption core accepts new plain text every 11 clocks.

The PLUG module is a silicon-proven AXI-to-AXI bridge designed to provide data encryption and inline ECC for reliable and secure communication.
It supports AXI4 protocol with bursts and integrates seamlessly into systems handling DMA, CPU, or cache streams.
For write transactions, it encrypts data and appends ECC, while for reads, it decrypts and validates/corrects ECC.

The ICE-IP-63 (EIP-63) is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES-CTR and GMAC on bulk data.
Its flexible data path is suitable to scale from 100 Gbps to 2.4 Tbps to provide a tailored engine with minimal area for your application.
The FIFO-like data interface makes it possible to perform frame processing for many different protocols, including MACsec, IPsec, and OTN security.

Throughput: 128 bit (16 Byte) wide encryption/decryption per cycle
Throughput: 1 tweak computation per 4 clock cycles
Bidirectional design including arbitration between read and write requests
Zero clock overhead for switching between encryption (write) and decryption (read)
30-40 cycle data channel latency

Performs encryption, decryption and/or authentication using AES Counter Mode (CTR) or Galois Counter Mode (GCM)
Supports AES key sizes 128 or 256
Internal key management with NIST-compliant key generation
Encrypt memory space into user-defined vaults, each with a unique key
Compatible with AMBA AXI4 interface
Supports hard or soft memory controllers in Xilinx FPGA and SoC devices
Supports multiprocessor systems

128/512-bit (16-byte) encryption and decryption per clock cycle throughput
Bidirectional design including separate crypto channels for read and write requests, ensuring non-blocking Read
Read-modify-write supporting narrow burst access.
Zeroization and support for memory initialization
Latency: <28 clock cycles for unloaded READ