Embedded vision processor IP

Multi-sensor interface with up to 20-bit linear video input
Up to 8 independent camera sources of max resolution 48 Megapixels / 8K (8192 x 6144)

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

2048/1024b Load/Store capabilities
1024 8-bit MAC: 2X MAC capability versus Vision Q7 DSP
8/16/32-bit fixed-point processing
Double-precision (FP64), single-precision (FP32), and half-precision (FP16) floating-point processing

Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets

Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
Future proof architecture that supports the most advanced ML data types and operators

The Intel FPGA Video and Image Processing Suite is a collection of Intel FPGA intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs
These Intel FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as studio broadcast, video conferencing, AV networking, medical imaging, smart city/retail, and consumer.

The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and FPGA technologies.
The MIPI CSI-2 implementation enables high-speed, low-power transmission of image data from camera modules to host processors.

Embedded Vision Processor IP