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Embedded Vision IP

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  • ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • Tensilica Vision Q7 DSP
    • Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets
    Block Diagram -- Tensilica Vision Q7 DSP
  • Tensilica Vision P6 DSP
    • 1024/512b Load/Store capabilities
    • 256 8-bit MAC
    • 8/16/32-bit fixed-point processing
    • Single-precision (FP32) and half-precision (FP16) floating-point processing
  • Tensilica Vision Q8 DSP
    • 2048/1024b Load/Store capabilities
    • 1024 8-bit MAC: 2X MAC capability versus Vision Q7 DSP
    • 8/16/32-bit fixed-point processing
    • Double-precision (FP64), single-precision (FP32), and half-precision (FP16) floating-point processing
  • UHD Image Signal Processing (ISP) Pipeline
    • Supports resolutions up to 7680x7680, including 4K2Kp60 (3840x2160)
    • Input video formats: Raw Bayer, RGB and YCbCr; 8/10/12-bit per color
    Block Diagram -- UHD Image Signal Processing (ISP) Pipeline
  • H.264/H.265 Video Codec Unit
    • Multi-standard encoding/decoding support, including:
  • Video Design Framework for Multi-camera Vision Applications
    • Complete video design framework for embedded multi-camera vision applications
    Block Diagram -- Video Design Framework for Multi-camera Vision Applications
  • ACAP HDR Image Signal Processing Framework
    • Complete HDR ISP video processing framework for multi-channel vision and AI systems
    • Demonstrates logicBRICKS HDR ISP pipeline for parallel processing of three UHD automotive video cameras
    • Fully compatible with Xylon logiIVID-ACAP-ISP HDR ISP Evaluation Kit for Versal ACAP based on AMD-Xilinx ACAP Versal VCK190 Evaluation Kit
    • Runs on Linux OS, includes logicBRICKS software drivers and demo applications made with AMD-Xilinx Vitis™ Unified Software Platform 2021.2
    Block Diagram -- ACAP HDR Image Signal Processing Framework
  • Image signal processor to advance vision systems for IoT and embedded markets
    • Multi-sensor interface with up to 20-bit linear video input
    • Up to 8 independent camera sources of max resolution 48 Megapixels / 8K (8192 x 6144)
    Block Diagram -- Image signal processor to advance vision systems for IoT and embedded markets
  • Full HD/UHD multi-stream video and vision integrated platform solution
    • Unified platform solution
    • Multi-standard video codecs
    • Embedded vision acceleration
    • Value-add image processing features
    Block Diagram -- Full HD/UHD multi-stream video and vision integrated platform solution
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