ETIS ORI 4.1.1 CPRI IQ Compression IP
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ETSI SSP I3C Interface
- The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Common Layer (SCL) protocol
- The use of the MIPI I3C Basic bus specification provides the ETSI SSP with a multitude of benefits, such as higher data rate, flexible and efficient information exchange, and strong integration of SSP in connected devices
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ETR101290 IP core (Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06))
- Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06)
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Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard
- fully integrated Single Wire Protocol (SWP) Slave Analog Front End (AFE)
- fully compliant with the ETSI TS 102 613 standard
- operating junction temperature range: -40°C to +125°C
- silicon proven in a 130 nm CMOS process
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Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard
- fully integrated Single Wire Protocol (SWP) Master Analog Front End (AFE)
- fully compliant with the ETSI TS 102 613 standard
- operating junction temperature range: -40°C to +125°C
- silicon proven in a 130 nm CMOS process
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ISO/IEC 7816-3 digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards
- fully compliant with the ISO/IEC 7816-3, ETSI TS 102 221 and EMV 2000 standards
- character protocol supported (T=0)
- block transmission protocol supported (T=1)
- clock stop mode supported
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Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard
- fully compliant with the ETSI 102.613 standard
- continuous bidirectional stream through eight physical buffers: four 32 bytes buffers for automatic frame emission; four 32 bytes buffers for automatic frame reception
- 256 bytes Dual Port RAM acting as a physical buffer
- total gate count smaller than 2.3 kgates (excluding RAM)
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APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer
- The LLL (Logical Link Layer) of the SWP protocol will be implemented in software. The SWP
- HW supports the following features:
- protocol in software.
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ISO 7816 based digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards
- Supports asynchronous T = 0 and T =1 transmission protocols
- Supports 2 –66 Mhz range for the input frequency
- Supports class A, B and class AB smart cards
- Timed interrupt for efficient support for synchronous protocol
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ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards
- fully compliant with the ISO/IEC 7816-3, EMV, GSM and WHQL standards
- character protocol supported (T=0)
- one transmit buffer and one receive buffer
- 11-bit Elementary Time Unit (ETU) counter
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Verification IP for Ethernet
- Avery TSN Ethernet Verification IP provides a complete simulation-based func tional verification solution for core-level and SoC-level verification, including MAC and PHY models, protocol checking, and optional compliance test suite based on UNH-IOL test specifications.
- Additional integration with ARM® Fast Model integration enables running the TSN IP’s software stack in one fully integrated testbench.
