ETIS ORI 4.1.1 CPRI IQ Compression IP
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121
IP
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ETSI SSP I3C Interface
- The I3C interface for the communication of an Smart Secure Platform(SSP), as defined in ETSI using the Smart Secure Platform Common Layer (SCL) protocol
- The use of the MIPI I3C Basic bus specification provides the ETSI SSP with a multitude of benefits, such as higher data rate, flexible and efficient information exchange, and strong integration of SSP in connected devices
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ETR101290 IP core (Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06))
- Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06)
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Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard
- fully integrated Single Wire Protocol (SWP) Slave Analog Front End (AFE)
- fully compliant with the ETSI TS 102 613 standard
- operating junction temperature range: -40°C to +125°C
- silicon proven in a 130 nm CMOS process
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Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard
- fully integrated Single Wire Protocol (SWP) Master Analog Front End (AFE)
- fully compliant with the ETSI TS 102 613 standard
- operating junction temperature range: -40°C to +125°C
- silicon proven in a 130 nm CMOS process
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ISO/IEC 7816-3 digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards
- fully compliant with the ISO/IEC 7816-3, ETSI TS 102 221 and EMV 2000 standards
- character protocol supported (T=0)
- block transmission protocol supported (T=1)
- clock stop mode supported
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Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard
- fully compliant with the ETSI 102.613 standard
- continuous bidirectional stream through eight physical buffers: four 32 bytes buffers for automatic frame emission; four 32 bytes buffers for automatic frame reception
- 256 bytes Dual Port RAM acting as a physical buffer
- total gate count smaller than 2.3 kgates (excluding RAM)
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APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer
- The LLL (Logical Link Layer) of the SWP protocol will be implemented in software. The SWP
- HW supports the following features:
- protocol in software.
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Voltage Detector
- High Accuracy: Voltage Detector IPs offer precise voltage monitoring with high accuracy, ensuring reliable performance in critical applications
- Low Power Consumption: Designed for energy efficiency, these IPs consume minimal power, making them ideal for battery-operated devices
- Wide Voltage Range: Capable of detecting a broad range of voltage levels, these IPs are versatile and suitable for various applications
- Fast Response Time: With rapid response times, Voltage Detector IPs provide timely alerts for voltage anomalies, enabling prompt corrective actions
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Power Switch
- High Efficiency: Optimizes power usage by controlling the supply to different system components as needed
- Low On-Resistance: Ensures minimal voltage drop and power loss when the switch is active
- Fast Switching Time: Provides rapid transition between on and off states, crucial for responsive power management
- Integrated Protection: Includes features like over-current, over-voltage, and thermal protection to ensure safe operation
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Low Dropout Regulator (LDO)
- High Efficiency: Operates efficiently even at low voltage differences, reducing power consumption and heat dissipation
- Fast Transient Response: Quickly responds to changes in load, maintaining a stable output voltage
- Low Noise: Minimizes output noise, crucial for sensitive analog and RF applications
- Protection Features: Includes over-current, over-temperature, and short-circuit protection to ensure reliability and safety