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ECC Accelerator IP

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Compare 55 IP from 18 vendors (1 - 10)
  • Asymmetric cryptographic accelerator
    • The ACrypto Engine is an asymmetric cryptographic accelerator suitable for embedded application.
    • It provides capability for basic arithmetic and frequently used operations. Along with driver, it is flexible to support popular upperlayer applications.
  • The FastMath Pack is a math processing accelerator for the ARC HS family
    • Achieves up to 3232 DMIPS and 6681 CoreMarks* at 1.61 GHz on 28HPM (single-core configuration, worst case silicon and conditions)
    • Delivers 2.13 DMIPS/MHz, 4.15 CoreMarks/MHz* (per core)
    • High-speed, 10-stage pipeline
    • Up to 16MB instruction and data close coupled memory (CCM)
    Block Diagram -- The FastMath Pack is a math processing accelerator for the ARC HS family
  • Agile PQC Public Key Accelerator
    • Agile IP comprised of HW/FW/SW, adaptable to future standards’ evolution
    • Highly configurable IP can be tuned for specific applications with most optimal PPA
    • Scalable PQC PKA IP complies with latest NIST PQC algorithms
  • Agile Post Quantum Crypto (PQC) Public Key Accelerator - NIST algorithms
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • Agile ECC/RSA Public Key Accelerator with 32-bit ALU
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • Agile ECC/RSA Public Key Accelerator with 128-bit ALU
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • Public Key Accelerator
    • Modular exponentiation operations with up to 4096-bit modulus
    • Prime field ECC operations with up to 571-bit modulus
    • Fastest implementation is 58 kGE and 68 Op/s for 2048-bit RSA, 431 Op/s for 1024-bit RSA, 150 Op/s for 384-bit scalar multiplication
    • Smallest implementation is 33 kGE and 67 Op/s for 1024-bit RSA, 24 Op/s for 384-bit scalar multiplication
    Block Diagram -- Public Key Accelerator
  • 32-bit Public Key Accelerator
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • 128-bit Public Key Accelerator
    • Offloads the computationally intensive parts of public key cryptography
    • Support for ARM® AMBA® AHB™/AXI™ and synchronous RAM interfaces
    • Integer operations (512-, 768-, 1024-, 1536-, 2048-, 3072-, and 4096-bit)
    • ECC-GF(p) operations (160, 192, 224, 256, 384, 512 and 521-bit)
  • Blockchain Hardware Accelerator
    • Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
    • Ideal for FPGA/ASIC integration
    Block Diagram -- Blockchain Hardware Accelerator
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Semiconductor IP