Datapath IP

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Compare 245 IP from 39 vendors (1 - 10)
  • SATA Bridge Platform (Optional: AES, Hardware Datapath)
    • Fully compliant to SATA 1.5Gb/s, 3Gb/s, and 6Gb/s specifications (SATA 3.3).
    • Independent host and device SATA speed negotiation.
    • Software extensible bridging platformCommand set support for Windows, along with standard Linux discovery and communication.
    • Boot Device Capable.
  • 100G Ethernet Verification IP
    • The 100G Ethernet Verification IP (VIP)  offers a robust and high-performance solution for validating the critical MAC-to-PCS datapath in 100 Gigabit Ethernet systems.
    • Designed to ensure protocol compliance, the VIP facilitates the generation, transmission, reception, and monitoring of various Ethernet MAC frame types, all while adhering to IEEE 802.3ba and related standards.
    • Whether you are working on IP, subsystem, or SoC-level verification, this VIP is your go-to solution for comprehensive Ethernet testing.
    Block Diagram -- 100G Ethernet Verification IP
  • 32-Bit Security processor
    • Nuclei Security processor is a series of chips designed specifically for security application scenarios, including NS100, NS300, and NS600 products.
    Block Diagram -- 32-Bit Security processor
  • Searchable Synchronous FIFO
    • The FIFO-CAM controls are designed to operate over a wide range of clock frequencies.
    • The interface signals are fully synchronous; no asynchronous signals are present on either side.
    • Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.
    Block Diagram -- Searchable Synchronous FIFO
  • 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
    • 2 different packages with or without vector: AX46MPV, AX46MP
    • in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
    • Symmetric multiprocessing up to 16 cores
    • Private Level-2 cache
    • Shared L3 cache and coherence support
    Block Diagram -- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
  • 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
    • AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension.
    • It supports RISC-V standard “G (IMA-FD)”, “ZC” compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector), CMO (cache management) extensions, Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions.
    Block Diagram -- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
  • MSP7-32 MACsec IP core for FPGA or ASIC
    • The MSP7 implementation fully supports the IEEE 802.1ae (MACsec) algorithm for 128-bit bit keys, including AES support in Galois Counter Mode (GCM) per NIST publication SP800-38D.
    • The core is designed for flow-through operation. MSP7 supports encryption and decryption modes (encrypt-only and decrypt-only options are available.
    Block Diagram -- MSP7-32 MACsec IP core for FPGA or ASIC
  • ISDB-T Modulator
    • The CMS0045 ISDB-T Modulator provides all the necessary processing steps to modulate one, two or three transport stream into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857/9957 or AD9789. Optionally the output can be selected as an IF to supply a single DAC.
    • The design has been optimised to provide excellent performance in low cost FPGA devices such as the Cyclone range from Altera or the Spartan range from Xilinx
    Block Diagram -- ISDB-T Modulator
  • RLDRAM II Controller Intel® FPGA IP
    • Support for industry-standard RLDRAM II components
    • Flexible and robust design
    • This IP is included in the IP Base Suite which is bundled with Intel® Quartus® Prime Standard and Pro Edition Software.
  • QDR II SRAM Controller Intel® FPGA IP Function
    • The QDR II SRAM Controller Intel FPGA IP provides an easy-to-use interface to QDR II SRAM and QDR II+ SRAM modules
    • The QDR II SRAM controller ensures that the placement and timing are in line with QDR II specifications
    • The QDR II SRAM controller’s local interface is compatible with the Intel FPGA Avalon® Memory-Mapped interface, for easy integration into Intel Qsys IP.
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Semiconductor IP