Data Flow Processor IP
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40
IP
from 27 vendors
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High Performance NVMe for PCIe-based storage
- NVM Express Compliant
- Automatic NVMe Command management
- Single I/O queue
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Fully Configurable Radix 2 FFT/IFFT Processor
- Radix-2 Fast Fourier Transform processor IP Core.
- Same IP core may be used to compute both FFT and IFFT transforms without any complexity overhead.
- Highly parameterizable/scalable design using generic I/O fixed point precision and generic internal calculations precision.
- Bit true Matlab script model is provided to aid core fixed point precision configuration for any target application.
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Low-Latency AVC/H.264 Baseline Profile Decoder Core
- Constrained Baseline Profile AVC/H.264 decoder
- Ultra-Low-Latency: less than one msec latency for most widely used formats
- High performance: 2.5 cycles per pixel; Full-HD capable
- Support
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Four-Wire slave IP for use with the Mentor M8051W and M8051EW
- Implementation of a four-wire synchronous full-duplex slave interface, compatible with the Motorola SPI bus.
- Supports various message protocols using byte granularity data.
- Programmable clock phase and clock and select polarity.
- Supports any four-wire clock rate, independent of microcontroller clock rate.
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Two-Wire slave IP for use with the Mentor M8051W and M8051EW
- Implementation of a two-wire slave interface, compatible with I2C bus standard
- Compatible with I2C Fast and Fast Mode plus signalling
- Supports seven and ten-bit addressing modes, with optional response to general call address
- Can implement flow control with stretching
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Two-Wire Slave Interface for M8051W and M8051EW Microcontrollers
- Implementation of a two-wire slave interface, compatible with I2C bus standard
- Compatible with I2C Fast and Fast Mode plus signalling
- Supports seven and ten-bit addressing modes, with optional response to general call address
- Can implement flow control with stretching
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Near-threshold voltage and ultra-wide dynamic voltage and frequency scaling (UW-DVFS)
- Elimination of static margins
- Operation at Near-Threshold Voltage (Minimum Energy Point)
- Minima UWDVFS covers all operating points, scaling accurately to the minimum voltage needed by the application.
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HiGig Ethernet MAC
- Compliant to the Broadcom HiGig and HiGig2 Protocol Definitions
- 64-bit wide internal data path operating at a maximum frequency of 187.5 MHz (LatticeECP3 maximum 156 MHz)
- XGMII interface to the PHY layer (using IODDR external to the core)
- XAUI interface to the PHY layer (using PCS/SERDES external to the core)
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10Gb+ Ethernet MAC
- Compliant to IEEE 802.3-2005 standard, successfully passed University of New Hampshire InterOperability Laboratory (UNH-IOL) 10GbE MAC hardware tests
- Supports standard 10Gbps Ethernet link layer data rate
- Supports rates up to 12Gbps by over-clocking
- 64-bit wide internal data path operating at 156.25MHz to 187.5MHz
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ASIP-2
- Platform to design Application Specific Instruction Set Processors (ASIPs).
- Ideal for supporting multi-standard systems.
- Supports a wide range of complex DSP functions.
- The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
