Data Flow Processor IP
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57
IP
from 28 vendors
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10)
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Graphics Processor Overlay IP Core
- Technology independent soft IP Core for FPGA, ASIC and SoC devices
- Supplied as human-readable VHDL (or Verilog) source code
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64-bit RISC-V Application Processor Core
- 64-bit RISC-V core
- Linux capable
- In-order 7-stage pipeline
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Cyber Escort Unit IP provides real time detection of sero day attacks on processor
- Hardware protection on processor
- Compliant with all processor families
- Escort step by step the program execution
- Protection against Cyber attack (ROP, JOP, Buffer overrun, etc.) and Fault Injection attack targeting the code execution
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Baseband processor
- The Ceva-BX2 baseband processor IP handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming.
- It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size.
- Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators.
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Near-threshold voltage and ultra-wide dynamic voltage and frequency scaling (UW-DVFS)
- Elimination of static margins
- Operation at Near-Threshold Voltage (Minimum Energy Point)
- Minima UWDVFS covers all operating points, scaling accurately to the minimum voltage needed by the application.
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Complete Neural Processor for Edge AI
- Designed for Low-Power Neural Network Processing
- Flexible Training Methods
- Scalable Neuron Fabric
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Image Signal Processor (5MP, 2X Sensors) IP
- Self-contained, no external memory needed
- ARM® Cortex-R4 CPU @500 MHz
- Up to 2 Mbytes of SRAM
- Up to 4 Mbytes of stacked Flash or 16 Mbyte external Flash with update via communication interfaces
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Unified Deep Learning Processor
- Unified deep learning/vision/video architecture enables flexibility
- Low power extends battery life and prevents overheating
- Single scalable architecture
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Scalable and flexible display processor
- Leading Performance per Area
- Extreme Low Power Design
- Display Output
- AXI bus Interfaces
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Configurable UART with FIFO, software and hardware flow control
- Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
- Configuration capability
- Separate configurable BAUD clock line
- Majority Voting Logic
