Cortex-M3 IP
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32 bit Microprocessor compatible to ARMv7-m ISA (Cortex-M3)
- compatible to ARMv7-M Instruction Set Architecture (Cortex-M3)
- single clock, static design
- single AMBA V2.0 AHB bus interface
- vectored interrupt controller
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32-bit RISC Processor To Deliver High Performance In Low-Cost Microcontroller Applications
- Powerful debug and non-intrusive real-time trace - Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug.
- Memory Protection Unit (MPU) - Software reliability improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data.
- Integrated nested vectored interrupt controller (NVIC) - There is no need for a standalone external interrupt controller. Interrupt handling is taken care of by the NVIC removing the complexity of managing interrupts manually via the processor.
- Thumb-2 code density - On average, the mix between 16bit and 32bit instructions yields a better code density when compared to 8bit and 16bit architectures. This has significant advantages in terms of reduced memory requirements and maximizing the usage of precious on-chip Flash memory.
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Tamper-resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M
- Tamper-resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M
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Arm Cortex-M33
- TrustZone for Armv8-M - A foundation for security for embedded devices. TrustZone offers software isolation to code, memory and I/O while retaining the requirements of embedded applications: real-time deterministic response, minimal switching overhead, and ease of software development.
- Co-processor interface - A dedicated bus for extending the operation of the processor with tightly coupled co-processors to handle frequent and compute intensive operations in an ecosystem friendly manner. The interface supports up to eight accelerators and takes into account the security state of the co-processor.
- SIMD, saturating arithmetic, fast MAC - Powerful instruction set for accelerating DSP applications, built right into the processor. A highly optimized DSP library built using these instructions is available free-of-charge from the Arm website (CMSIS Library).
- Memory Protection Unit (MPU) - Software reliability and system security improves when each module is allowed access only to specific areas of memory required for it to operate. This protection prevents unexpected access that may overwrite critical data. Each of the security zones can have a dedicated MPU that may be configured with a different number of regions.
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Secure AHB Performance Subsystem - ARM M3
- Quick development start up
- Low power plus performance to handle most IoT software
- Integration and software support available
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Telematics Processors IP
- Core and infrastructure
- ? ARM® Cortex™-R4 MCU
- ? Embedded SRAM
- ? SDRAM controller
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Secure key computation, encryption, decryption, signature and verification functionalities compliant with the PKCS#1
- key generation, encryption, decryption, signature and verification functions
- fully compliant with the PKCS#1 standards
- all key sizes supported up to 8192 bits
- core functions ASM-optimized for the targeted processor
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Cryptographic library for Elliptic Curve Diffie–Hellman (ECDH) and Elliptic Curve Digital Signature Algorithm (ECDSA)
- all ANSI standard curves supported
- all NIST standard curves supported
- ECDSA key generation, signature and verification
- ECDH key generation and common key functions
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Java Card compliant cryptographic library for encryption and decryption of RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- key generation, encryption, decryption, signature and verification functions
- all key sizes supported up to 8192 bits
- core functions ASM-optimized for the targeted processor
- configurable architecture: adjustable trade-off between performance and RAM footprint; dedicated coprocessor available separately (about 10 times faster)