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Cadence PCIe IP

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Compare 23 IP from 1 vendors (1 - 10)
  • PCI Express (PCIe) 2.1 Controller
    • Compliant with PCIe 2.1 and 1.1 specifications
    • Configurable as Root Complex, Endpoint, or Dual Mode
    • Ultra-low transmit/receive latency and high bandwidth
    • Supports x1, x2, x4, x8, and x16 configurations
  • PCI Express (PCIe) 3.1 Controller
    • Compliant with PCIe 3.1, 2.1, and 1.1 specifications
    • Configurable as Root Complex, Endpoint, or Dual Mode
    • Ultra-low transmit/receive latency and high bandwidth
    • Supports x1, x2, x4, x8, and x16 configurations
  • PCI Express (PCIe) 4.0 Controller
    • Compliant with PCIe 4.0, 3.1, 2.1, and 1.1 specifications
    • 32/16b interface for 500MHz or 1GHz core operation
    • Modes supported: Root Complex, EndPoint, or Dual Mode
    • SR-IOV and multifurcation options
  • PCI Express (PCIe) 5.0 Controller
    • Compliant with PCIe 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
    • 32/16b interface for 500MHz or 1GHz core operation
    • Modes supported: Root Complex, EndPoint, or Dual Mode
    • SR-IOV and multifurcation options
  • PHY for PCIe 6.0 and CXL for Samsung SF5A
    • DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
    • Low active and standby power consumption, supports L1 sub-states standby power management
    • Extensive set of isolation, test modes, and loopbacks including APB and JTAG
    • Supports lane aggregation and bifurcation
  • PCIe 4/3/2 SerDes PHY - Samsung 14nm
    • Duplex lane configurations of x2, x4, and x35
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 12nm
    • Duplex lane configurations of x2, x4, and x35
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • PCIe 4/3/2 SerDes PHY - GLOBALFOUNDRIES 22nm
    • Duplex lane configurations of x2, x4, and x35
    • Transmit swing of at least 800mV differential peak-to-peak for MR & LR, 360mv for SR
    • Support for AC-coupled interfaces
    • Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
  • 10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
    • Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, QSGMII,and SGMII
    • Supports PCIe L1 sub-states
    • Supports SRIS and internal SSC generation
    • Multi-protocol support for simultaneous independent links
  • 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
    • Support for PCIe 1.1, 2.1, and 3.0
    • Supports x1 configuration
    • Compliant to PIPE 4.2 specification with configurable PIPE frequency
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