CXL 2.0 IP
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91
IP
from 9 vendors
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Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- Supports the latest CXL specification
- AMBA AXI Layer for CXL.io
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Compute Express Link (CXL) 2.0 Controller
- Supports the CXL 2.0 specification
- Implements the CXL.io, CXL.mem, and CXL.cache protocols
- Supports all 3 defined CXL device types
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CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
- Supports all required features of CXL 3.1 and CXL 3.0
- Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
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CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge + LTI and MSI-GIC interfaces
- Supports all required features of CXL 3.1 and CXL 3.0
- Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
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CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge
- Supports all required features of CXL 3.1 and CXL 3.0
- Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
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CXL 2.0 Premium Controller Device/Host/DM 512b
- Supports all required features of CXL 3.1 and CXL 3.0
- Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
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CXL 2.0 Integrity and Data Encryption Security Module
- Compliant with the CXL 2.0 IDE specifications for CXL.cache/mem
- Compliant with PCI Express IDE specification for CXL.io
- High-performance AES-GCM based packet encryption, decryption, authentication
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CXL 2.0 Dual Mode Controller
- Compatible with CXL 2.0 specification and backward compatible with CXL V1.0 and CXL V1.1
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CXL 2.0 Retimer
- Compliant with CXL 2.0 spec.
- Compliant with PCIE Gen5/4 Specs.
- Forward mode supported.
- X1,X2,X4,X8,X16 lanes supported.
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PHY for PCIe 6.0 and CXL for Samsung SF5A
- DSP-based Long Reach (LR) equalization and clock data recovery (CDR) provide superior performance and reliability
- Low active and standby power consumption, supports L1 sub-states standby power management
- Extensive set of isolation, test modes, and loopbacks including APB and JTAG
- Supports lane aggregation and bifurcation