CCSDS LDPC Fordward Error Correction IP
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5
IP
from 2 vendors
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5)
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CCSDS 231.0 LDPC(128, 64) and LDPC(512, 256) Encoder and Decoder
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
- Low implementation loss
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LDPC CCSDS (8160, 7136) Encoder and Decoder
- Fully synchronous design
- Fully synthesizable
- Optimized for high performance and low resources
- Low implementation loss
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CCSDS AR4JA LDPC Encoder and Decoder with code rates 1/2, 2/3, 4/5 and block sizes 1K, 4K, 16K
- Fully synchronous design, using single clock
- Fully synthesizable drop-in module for FPGAs
- Optimized for high performance and low resources
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CCSDS AR4JA LDPC Encoder & Decoder
- Gains up to 3 dB compared to Viterbi decoders.
- Low-power and low-complexity design.
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CCSDS 231.0 LDPC Encoder and Decoder
- Support for code rate 1/2
- Uncoded block sizes of 64 and 256 bits