Automotive RISC-V IP
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14
IP
from 9 vendors
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10)
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AI-Enabled RISC-V Automotive CPU for ADAS and Autonomous Vehicles
- High-performance 64-bit RISC-V application processor
- 2-way simultaneous multi-threading
- ASIL-B capable safety element out context
- Tightly-coupled accelerator interfaces
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32-bit RISC-V processor specifically designed for the Automotive and Functional Safety markets
- 32-bit RISC-V ISA
- ASIL B and ASIL D area optimised product variants
- Functional Safety Package and Independent Assessment
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Integrated Secure Element (iSE) for automotive
- Services:
- Secure Boot
- Secure Firmware update
- Life-cycle management
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RT-645 Embedded Hardware Security Module (HSM) for Automotive ASIL-D
- Custom-designed 32-bit RISC-V secure processor
- Security model include hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
- Standard hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator, AXI Multi Issue Out-of-Order, and Fast DMA capability. Additional algorithms such as Whirlpool (SHE), SHA-1 (legacy), AES-CMAC, SHA-3, Poly1305, ChaCha and OSCCA SM2-3-4 are available
- Multi-layered security model protects all core componentsagainst a wide range of attacks
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RT-640 Embedded Hardware Security Module (HSM) for Automotive ASIL-B
- Custom-designed 32-bit RISC-V secure processor
- Security model include hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
- Standard hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator, AXI Multi Issue Out-of-Order, and Fast DMA capability. Additional algorithms such as Whirlpool (SHE), SHA-1 (legacy), AES-CMAC, SHA-3, Poly1305, ChaCha and OSCCA SM2-3-4 are available
- Multi-layered security model protects all core components against a wide range of attacks
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
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32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV32I Base RISC-V ISA
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64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV64I Base RISC-V ISA
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Integrated Secure Element (iSE) for multiple applications
- Services:
- Secure Boot
- Secure Firmware update
- Life-cycle management
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Turnkey UWB MAC and PHY platform IP, for FiRa 2.0, CCC Digital Key 3.0, and Radar
- MAC and PHY with support of enhanced ranging and security based on IEEE 802.15.4z HRP in accordance with the FiRa Consortium requirements
