Automotive RISC-V IP
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21
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Data Movement Engine - Best in class multi-core high-performance AI-enabled RISC-V Automotive CPU for ADAS, AVs and SDVs
- The only Multi-Threaded Out-of-Order RISC-V Core with ASIL-B Certification
- Highly scalable multi-core, multi-cluster, coherent computing solution
- MIPS extensions for improved performance and functionality
- Use in Automotive, Datacenter, and Embedded applications
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32-bit RISC-V processor specifically designed for the Automotive and Functional Safety markets
- 32-bit RISC-V ISA
- ASIL B and ASIL D area optimised product variants
- Functional Safety Package and Independent Assessment
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Embedded Hardware Security Module (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
- The RT-64x Embedded Hardware Security Module (Root of Trust) family are fully programmable, ISO 26262 ASIL-B hardware security cores offering security by design for automotive applications.
- They protect against a wide range of failures such as permanent, transient and latent faults and hardware and software attacks with state-of-the-art anti-tamper and security techniques.
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8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
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32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
- Flexible use cases
- roven technology
- State-of-the-art safety and security
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32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
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32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV32I Base RISC-V ISA
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64-bit RISC-V CPU with M, Zicsr extensions and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV64I Base RISC-V ISA
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Integrated Secure Element (iSE) for automotive
- Services:
- Secure Boot
- Secure Firmware update
- Life-cycle management
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Embedded HSM Family (Root of Trust) - Automotive Grade ISO 26262 ASIL-B
- Custom-designed 32-bit RISC-V secure processor
- Security model include hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
- Standard hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator, AXI Multi Issue Out-of-Order, and Fast DMA capability. Additional algorithms such as Whirlpool (SHE), SHA-1 (legacy), AES-CMAC, SHA-3, Poly1305, ChaCha and OSCCA SM2-3-4 are available
- Multi-layered security model protects all core components against a wide range of attacks
