Agile analog IP

The agileTGLITCH temperature monitor provides security and protection against side-channel attacks (SCAs) and tampering such as over/under temperature attacks and temperature glitching.
The sensor provides digital outputs to warn (secure) processors of intrusion attempts. As a key part of the agileSCA TVC (Temperature, Voltage, Clock) security sensor can be tuned to your specifications.

The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.

The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
The agileSensorIF Subsystem enables easy interaction with the analog world.

The agileVGLITCH voltage monitor provides security and protection against voltage side-channel attacks (SCA) and tampering such as supply voltage changes/glitches and power supply manipulation.
The sensor provides digital outputs to warn (secure) processors of intrusion attempts, thus enabling a holistic approach to hardware security.

The agileTSENSE_A GP Temperature Sensor is a traditional ΔV_BE temperature sensor that amplifies the difference between two V_BE voltages, and converts the result to a single-ended signal.
This temperature sensor can be used with the agileADC in order to provide a digital output with an overall relative accuracy of +/-0.25°C.
On modern SoCs, thermal management is critical for detection of security attacks and optimization of power, performance and area.

The agileREF consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica current generators and bias current generators.
The number of output bias currents can be specified up to a maximum of 16 configurable outputs.
There is an integrated test bus.

The agileRCOSC is based on a traditional architecture which allows for the frequency to be trimmed to remove the effects of process variation.
This can also be configured as a Free Running Clock (FRC) where a high accuracy clock is not required.

The agilePOR GP is a Power-On-Reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.

The agileLDO_LP is a linear regulator, suitable for use in any low power, low current system and is designed to provide a flexible range of regulated output voltages suitable for ultra-low power systems and near-vt operating modes.
The agileLDO_LP consists of: A voltage reference generator, an error amplifier and a output current source. The regulated output voltage is fed-back into the error amplifier to maintain a constant regulated output over the specified range of input voltages and load currents.

Agile Analog IP