Acceleration Engine IP
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54
IP
from 20 vendors
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10)
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CAN-SEC Acceleration Engine
- CAN-XL Protocol (CiA 610-1)
- CAN-XL Addon Part-1 (CiA 613-1)
- CAN-XL Addon Part-2 Security (CiA-613-2)
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CANsec Acceleration Engine
- CANsec Acceleration Engine
- Easy to Integrate
- Straightforward to Implement
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High-performance 64-bit RISC-V architecture multi-core processor with AI vector acceleration engine
- Instruction set: RISC-V RV64GC/RV 64GCV;
- Multi-core: Isomorphic multi-core with 1 to 4 optional clusters. Each cluster can have 1 to 4 optional cores;
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High-performance 32-bit multi-core processor with AI acceleration engine
- Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
- Multi-core: Isomorphic multi-core, with 1 to 4 optional cores;
- Pipeline: 12-stage;
- Microarchitecture: Tri-issue, deep out-of-order;
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2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
- Vertically integrated HW + SW solution
- Monolithique HW building block, open to any system integration. Can be associated with any companion IP:
- 2 hardware versions:
- Software ported on numerous processors and OS
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MACsec Engine, 1G to 25G, Full Duplex, Integrated
- CLASSIFICATION
- MACsec PROCESSING FEATURES
- INGRESS PATH CONSISTENCY CHECKING
- MISCELLANEOUS
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Powerful vector DSP for 5G-Advanced Massive Compute
- Designed to meet the demanding requirements of modern 5G and 5G-Advanced networks
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Secure Boot Hardware Engine
- Protection Layers
- Public-Key Authentication Benefits
- Fast & Compact
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Convolutional Neural Network (CNN) Compact Accelerator
- Support convolution layer, max pooling layer, batch normalization layer and full connect layer
- Configurable bit width of weight (16 bit, 1 bit)
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LPDDR5X/5/4X PHY in TSMC (N5, N4P, N3E)
- Low latency, small area, low power
- Compatible with JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs up to 8533 Mbps
- DFI 5.0 compliant interface to the memory controller
- DFI Frequency Ratio Support: DFI 1:1:4, 1:1:2 modes (DFICLK:CK:WCK)