IP Catalog > AXI Bridge

AXI Bridge IP

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Compare 151 IP from 24 vendors (1 - 10)
  • AHB Lite to AXI Bridge
    • The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
    • It is expected that the AXI clock and the AHB clock are derived from the same clock source, and that the period of the AHB Lite clock is an integer multiple of the AXI clock in the range [1,16].
    Block Diagram -- AHB Lite to AXI Bridge
  • SPI Slave To AXI Bridge IIP
    • Compliant with the SPI Block Guide 4.01 standard.
    • Full SPI Slave functionality.
    • Converts SPI Transactions into AXI write or read instructions
    • Allows external devices to access the internal AXI Bus
    Block Diagram -- SPI Slave To AXI Bridge IIP
  • MIPI SPMI Slave AXI Bridge IIP
    • Supports 2.0 and 1.0 MIPI SPMI Specification
    • Full MIPI SPMI Slave functionality
    • Allows external devices to access the internal AXI Bus
    • Supports following frames
    Block Diagram -- MIPI SPMI Slave AXI Bridge IIP
  • MIPI I3C Slave To AXI Bridge IIP
    • Compliant with the I3C version 2.0 specification.
    • Full MIPI I3C Slave functionality.
    • Convert MIPI I3C Transactions into AXI write or read instructions
    • Allows external devices to access the internal AXI Bus
    Block Diagram -- MIPI I3C Slave To AXI Bridge IIP
  • JTAG Slave To AXI Bridge IIP
    • Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6
    • Supports all the JTAG tap instructions.
    • Supports programmable clock frequency of operation.
    • Supports Instruction register and data register of various sizes.
    Block Diagram -- JTAG Slave To AXI Bridge IIP
  • I2C Slave To AXI Bridge IIP
    • Compliant with I2C version 6.0 specification
    • Full I2C Slave Functionality
    • Converts I2C Transactions into AXI write or read instructions
    • Allows external devices to access the internal AXI Bus
    Block Diagram -- I2C Slave To AXI Bridge IIP
  • PCI Express to AMBA 4 AXI/3 AXI Bridge
    • Complete IP solution consists of digital controllers, PHYs and verification IP
    • Fully supports the Synopsys Controller IP for PCI Express Endpoint, Root Port, Dual Mode (EP/RP), and Switch port types
    • Fully compliant with the AMBA 3 AXI and 4 AXI interconnects
    • Full protocol mapping from PCI Express to the AMBA 3 AXI or 4 AXI bus protocol
    Block Diagram -- PCI Express to AMBA 4 AXI/3 AXI Bridge
  • SPI to AXI Bridge
    • The SPI to AXI Bridge IP core is commonly used as a monitor interface to allow external devices to access the internal AXI bus.
    • A SPI to AXI Bridge provides read/write access by an external SPI device to the various memories and registers that are present in the chip’s internal AXI subsystem via an AXI Master component interface.
    Block Diagram -- SPI to AXI Bridge
  • AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
    • Maximum Payload Size (MPS) up to 256 Bytes
    • Messaged Signaled Interrupt (MSI)
    • Memory mapped AXI4 access to PCIe space
    • PCIe access to memory mapped AXI4 space
  • RapidIO to AXI Bridge (RAB)
    • The RapidlO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP used along with the native RapidlO Controller (GRIO) to provide RapidlO interface on one side and AXI interface on the system side.
    • The Bridge has been architectured to interface with a RapidlO controller used as a Host or device.
    • The RIO-AXI BRIDGE uses high speed multi-channel DMA Messaging and data streaming controllers to match the bandwidth requirements of the RIO solution.
    Block Diagram -- RapidIO to AXI Bridge (RAB)
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