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AXI Bridge IP

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Compare 110 IP from 25 vendors (1 - 10)
  • RapidIO to AXI Bridge (RAB)
    • Compliant with RapidIO specification, Revision 4.0
    • Compliant to AMBA AXI protocol v4
    • Supports 32-bit or 38-bit addressing
    • AXI PIO operation with configurable number of AXI Slaves
    Block Diagram -- RapidIO to AXI Bridge (RAB)
  • SPI Slave to AXI Bridge
    • AMBA® AXI Monitor
    • Allows external devices to access the internal AXI Bus
    • AXI Master Read/Write capability
    • Useful for updating device software from and external device
    Block Diagram -- SPI Slave to AXI Bridge
  • PCIe 5.0 Premium Controller with AXI bridge & Advanced HPC Features (Arm CCA)
    • Designed to meet all required features of the PCI Express 6.0 (64 GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s) and 1.1 (2.5 GT/s), and PIPE specifications
  • MIPI SPMI Slave AXI Bridge IP
    • Supports 2.0 and 1.0 MIPI SPMI Specification
    • Full MIPI SPMI Slave functionality
    • Allows external devices to access the internal AXI Bus
    • Supports following frames
  • SPI Slave To AXI Bridge IP
    • Compliant with the SPI Block Guide 4.01 standard.
    • Full SPI Slave functionality.
    • Converts SPI Transactions into AXI write or read instructions
    • Allows external devices to access the internal AXI Bus
  • MIPI I3C Slave To AXI Bridge IP
    • Compliant with the I3C version 2.0 specification.
    • Full MIPI I3C Slave functionality.
    • Convert MIPI I3C Transactions into AXI write or read instructions
    • Allows external devices to access the internal AXI Bus
  • I2C Slave To AXI Bridge IP
    • Compliant with I2C version 6.0 specification
    • Full I2C Slave Functionality
    • Converts I2C Transactions into AXI write or read instructions
    • Allows external devices to access the internal AXI Bus
  • AHBlite to AXI Bridge
    • An interface (bridge) between the AHB domain and AXI domain
    • SINGLE/INCR/WRAP type write transactions
    • SINGLE/INCR/WRAP type read transactions
    • WRAP type transactions for word size accesses only. WRAP for half word and byte size accesses are not supported in this release
  • AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
    • Maximum Payload Size (MPS) up to 256 Bytes
    • Messaged Signaled Interrupt (MSI)
    • Memory mapped AXI4 access to PCIe space
    • PCIe access to memory mapped AXI4 space
  • AHB Lite to AXI Bridge
    • Supports 1:1 (AXI:AHB) synchronous clock ratio
    • AHB and AXI data widths are the same and either 32 or 64 bit based on the configuration
    • Supports narrow transfers on the AHB interface
    • Supports burst termination on the AHB during which dummy transfers are initiated on the AXI interface
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