ASIL-B IP
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128
IP
from 12 vendors
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10)
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RT-640 Embedded Hardware Security Module (HSM) for Automotive ASIL-B
- Custom-designed 32-bit RISC-V secure processor
- Security model include hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
- Standard hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator, AXI Multi Issue Out-of-Order, and Fast DMA capability. Additional algorithms such as Whirlpool (SHE), SHA-1 (legacy), AES-CMAC, SHA-3, Poly1305, ChaCha and OSCCA SM2-3-4 are available
- Multi-layered security model protects all core components against a wide range of attacks
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ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- VESA DSC 1.1 compliant
- Supports all DSC 1.1 mandatory encoding mechanisms
- Configurable maximum display resolution
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MIPI DPHY_RX v1.2, 1C2D, TSMC 16FFC, E/W orientation (ASIL-B)
- Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
- Supports MIPI DSI and CSI-2 protocols
- Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
- Supports LS data rate of 10Mbps and Ultra-low power modes
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MIPI DPHY_RX v1.2, 2C4D, TSMC 16FFC, E/W orientation (ASIL-B)
- Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
- Supports MIPI DSI and CSI-2 protocols
- Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
- Supports LS data rate of 10Mbps and Ultra-low power modes
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MIPI DPHY_TX v1.2, 1C2D, TSMC 16FFC, E/W orientation (ASIL-B)
- Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
- Supports MIPI DSI and CSI-2 protocols
- Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
- Supports LS data rate of 10Mbps and Ultra-low power modes
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MIPI DPHY_TX v1.2, 1C4D, TSMC 16FFC, E/W orientation (ASIL-B)
- Compliant with MIPI D-PHY specification up to v1.2/v1.1 (by different process nodes)
- Supports MIPI DSI and CSI-2 protocols
- Supports HS data rates up to 2.5Gbps (v1.2, per lane) . 1.5Gbps(v1.1, per lane)
- Supports LS data rate of 10Mbps and Ultra-low power modes
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CAN 2.0, CAN FD - Developed as ISO26262-10 Safety Element out of Context (ISO26262 soft IP SEooC, ASIL-B ready design)
- Designed in accordance to ISO 11898-1:2015
- Supports CAN 2.0B and CAN FD frames
- Support up to 64 bytes data frames
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ASIL-B Ready ISO 26262 Certified VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1 .4 compliant
- Reed-Solomon RS (254, 250) FEC, 10-bit symbols
- Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
- Includes the DisplayPort main 86/1Ob encoder
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eUSB2 v1.1 Dual-Role, repeater/native mode PHY, TSMC N5A, 1.2V, N/S orientation (ASIL-B)
- Fully compliant with Embedded Universal Serial Bus 2.0 (eUSB) electrical specification
- Compliant with UTMI+ specifications (High-speed, Full-speed, and Low-speed functions)
- Support clock inputs from 10/12/25/30/19.2/24/32/38.4MHz clock source
- Support repeater and native modes
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USB2.0 Dual-Role PHY, TSMC 16FFC, N/S orientation, type-C (ASIL-B)
- Smallest USB 2.0 PHY IP worldwide (IP size of 55nm, 40nm, 28nm, and 16/12nm are less than 0.2mm2)
- Fully compliant with Universal Serial Bus (USB) 2.0 electrical specification
- Compliant with UTMI+ specifications (High-Speed, Full-Speed, and Low-Speed functions)
